Clock.ProgUserClock.ucf

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## Xilinx User Constraint File (UCF)
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##	Board:					Xilinx - Kintex 7 KC705
##	FPGA:						Xilinx Kintex 7
##		Device:				XC7K325T
##		Package:			FFG900
##		Speedgrade:		-2
##
##	Notes:
##		Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V)
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## Clock Sources
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## User Clock
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##		Bank:						15
##			VCCO:					2.5V (VCC2V5_FPGA)
##		Location:				U45 (SI570)
##			Vendor:				Silicon Labs
##			Device:				SI570BAB0000544DG
##			Frequency:		10 - 810 MHz, 50ppm
##			Default Freq:	156.250 MHz
##			I²C-Address:	0x5D #$ (0111 010xb)
NET "KC705_ProgUserClock_p"				LOC = "K28";									## {IN}		U45.4
NET "KC705_ProgUserClock_n"				LOC = "K29";									## {IN}		U45.5
NET "KC705_ProgUserClock_p"				IOSTANDARD = LVDS_25;
NET "KC705_ProgUserClock_p"				TNM_NET = "PIN_ProgUserClock";