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Copy pathEthernetPHY.RGMII.ucf
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EthernetPHY.RGMII.ucf
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##
## single-ended, parallel TX path
NET "ML505_EthernetPHY_TX_Valid" LOC = "AJ10"; ## {OUT} U16.16; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_Error" LOC = "AJ9"; ## {OUT} U16.13; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<0>" LOC = "AF11"; ## {OUT} U16.18; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<1>" LOC = "AE11"; ## {OUT} U16.19; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<2>" LOC = "AH9"; ## {OUT} U16.20; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<3>" LOC = "AH10"; ## {OUT} U16.24; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_*" IOSTANDARD = LVCMOS25;
NET "ML505_EthernetPHY_TX_*" SLEW = FAST;
##
## single-ended, parallel RX path
NET "ML505_EthernetPHY_RX_Valid" LOC = "E32"; ## {IN} U16.4; Bank 11
NET "ML505_EthernetPHY_RX_Error" LOC = "E33"; ## {IN} U16.8; Bank 11
NET "ML505_EthernetPHY_RX_DATA<0>" LOC = "A33"; ## {IN} U16.3; Bank 11
NET "ML505_EthernetPHY_RX_DATA<1>" LOC = "B33"; ## {IN} U16.128; Bank 11
NET "ML505_EthernetPHY_RX_DATA<2>" LOC = "C33"; ## {IN} U16.126; Bank 11
NET "ML505_EthernetPHY_RX_DATA<3>" LOC = "C32"; ## {IN} U16.125; Bank 11
NET "ML505_EthernetPHY_RX_*" IOSTANDARD = LVCMOS25;
NET "ML505_EthernetPHY_RX_*" SLEW = FAST;
##
## Timing names
NET "ML505_EthernetPHY_RX_Clock" TNM_NET = "TGRP_EthernetPHY_RX_Clock";
NET "ML505_EthernetPHY_RX_Data[?]" TNM = "EthernetPHY_RX";
NET "ML505_EthernetPHY_RX_Valid" TNM = "EthernetPHY_RX";
NET "ML505_EthernetPHY_RX_Error" TNM = "EthernetPHY_RX";
##
## RX clock frequency
TIMESPEC "TS_EthernetPHY_RX_Clock" = PERIOD "TGRP_EthernetPHY_RX_Clock" 125 MHz HIGH 50%;
##
## according to IEEE 802.3 clause 35.4.2.3:
## t_SETUP(RCVR) = 2.0 ns
## t_HOLD(RCVR) = 0.0 ns
TIMEGRP "EthernetPHY_RX" OFFSET = IN 2.0 VALID 2.0 ns BEFORE "ML505_EthernetPHY_RX_Clock" RISING;