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Default.ucf
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## =============================================================================================================================================================
## Xilinx User Constraint File (UCF)
## =============================================================================================================================================================
## Board: Xilinx - Zynq ZC706
## FPGA: Xilinx Zynq 7000
## Device: XC7Z045
## Package: FFG900
## Speedgrade: -2
##
## Notes:
## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V)
##
## =============================================================================================================================================================
## Miscellaneous
## =============================================================================================================================================================
CONFIG PART = XC7Z045-FFG900-2;