Merge pull request #72 from BlockScience/push

Push

Author: SeanMcOwen

V1 Architecture/Class/Methods 1.md

@@ -0,0 +1,25 @@
+## System Methods
+
+- isValid: system $\rightarrow$ Bool
+- isDirected: system $\rightarrow$ Bool
+- isConnected: system $\rightarrow$ Bool
+- isDynamical: system $\rightarrow$ Bool
+- getOpenPorts: system $\rightarrow$ List[Terminal] = List[\{Processor, Index, Type\}]
+- getAvailableTerminals: system $\rightarrow$ List[Terminal] = List[\{Processor, Index, Type\}]
+- getConnectedComponents: system $\rightarrow$ List[System]
+- getSubsystems: system $\rightarrow$ List[Processor] (subset of the processor list which isSubsystem)
+- getHierarchy: system $\rightarrow$ NestedDict (primitive processors are leaves in this tree)
+- getSpaces: system $\rightarrow$ List[Space]
+- makeProcessor:system x block x List[wires] $\rightarrow$ Processor
+- Imp: system $\rightarrow$ Processor (aka "lazy make processor)
+
+## Processor Methods
+
+- isSubsystem: processor $\rightarrow$ Bool
+- isPrimitive: Process $\rightarrow$ Bool
+- getSystem: processor $\rightarrow$ System
+- getShape: processor $\rightarrow$ Block
+
+## Project Methods
+
+- lazyLoadCompositeProcessor

V1 Architecture/Schemas/Nested Schema 3.canvas

@@ -0,0 +1,31 @@
+{
+	"nodes":[
+		{"id":"b6fab004d256f8de","type":"text","text":"# Project\nComponents:\nToolbox\nWorkbench","x":-190,"y":-430,"width":160,"height":160},
+		{"id":"3df945f3f7d36b92","type":"text","text":"# Workbench\nComponents:\nList[Processor]\nList[Wire]\nList[System]","x":-30,"y":-230,"width":285,"height":160},
+		{"id":"3d7dedce274a492e","type":"text","text":"# Toolbox\nComponents:\nList[Block]\nList[Space]","x":-350,"y":-230,"width":160,"height":160},
+		{"id":"630f2a5feaf2fb22","type":"text","text":"# Processor\n\n**NOTE**: Subsystem is optional and if present turns it into a composite processor representing a system\n\nID: string (required) \n\nName: string (required) \n\nDescription: string \n\nParent: BlockID (required)\n\nPorts: array[Space.ID] \n\nTerminals: array[Space.ID] (required) \n\nSubsystem: { System ID: System.ID (required) Wires: array[string] (required) }","x":-150,"y":-30,"width":263,"height":590},
+		{"id":"110e3e478c6c326c","type":"text","text":"# System\n\nID: string (required)\n\nName: string (required) \n\nDescription: string \n\nProcessors: array[Processor.ID] (required) \n\nWires: array[Wire.ID] (required)","x":390,"y":-30,"width":310,"height":590},
+		{"id":"ae7731c5dabfb8ce","type":"text","text":"# Wire\n\nID: string (required) \n\nParent: Space.ID (required) \n\nSource:  { Processor: Processor.ID, \nIndex: integer } \n\nTarget:  { Processor: Processor.ID,\nIndex: integer }","x":135,"y":-30,"width":225,"height":590},
+		{"id":"a0eb3ee9cbb2cdd3","type":"text","text":"Similar to nodes (typed by blocks)","x":-150,"y":620,"width":263,"height":60,"color":"3"},
+		{"id":"e135c0917ca5d3a8","type":"text","text":"Similar to edges (typed by spaces)","x":135,"y":620,"width":225,"height":60,"color":"3"},
+		{"id":"f2682c67d9b9edff","type":"text","text":"Similar to Typed Multi-Digraphs
with extra rules
* ports can only be used once
* terminals can be used any number of times","x":390,"y":590,"width":310,"height":110,"color":"3"},
+		{"id":"3e2434525fcc8541","type":"text","text":"- Project can be thought of as your working directory \n- Each level down in the actual schema refers to nesting, i.e. a project has one toolbox and this one toolbox has a list of blocks and a list of spaces which follow the schemas described under it","x":-810,"y":-450,"width":380,"height":200,"color":"3"},
+		{"id":"2575ee7921d36820","type":"text","text":"# Block\n\n{ ID: string (required)\n\nName: string (required) \n\nDescription: string\n\nDomain: array[Space.ID] (required) \n\nCodomain: array[Space.ID] (required) }","x":-880,"y":-30,"width":200,"height":590},
+		{"id":"ae9da3db023837af","type":"text","text":"# Space\n\n{ ID: string (required) \n\nName: string (required) \n\nDescription: string }","x":-655,"y":-30,"width":165,"height":590},
+		{"id":"11cab3f937d7e1eb","type":"text","text":"# Architecture\n\n- Future component that will be an abstract representation of a system\n- To be implemented much later after dogfooding","x":-470,"y":-30,"width":240,"height":590,"color":"1"}
+	],
+	"edges":[
+		{"id":"0980aa1c29d50d33","fromNode":"b6fab004d256f8de","fromSide":"bottom","toNode":"3d7dedce274a492e","toSide":"top"},
+		{"id":"7b72b0c4fb473461","fromNode":"b6fab004d256f8de","fromSide":"bottom","toNode":"3df945f3f7d36b92","toSide":"top"},
+		{"id":"d32d2f9521cbe7e2","fromNode":"3df945f3f7d36b92","fromSide":"bottom","toNode":"630f2a5feaf2fb22","toSide":"top"},
+		{"id":"72a268db645b3f47","fromNode":"3df945f3f7d36b92","fromSide":"bottom","toNode":"ae7731c5dabfb8ce","toSide":"top"},
+		{"id":"f81624a9699cd0ba","fromNode":"3d7dedce274a492e","fromSide":"left","toNode":"2575ee7921d36820","toSide":"top"},
+		{"id":"6110bad326407cae","fromNode":"3df945f3f7d36b92","fromSide":"right","toNode":"110e3e478c6c326c","toSide":"top"},
+		{"id":"934ba36f96e6eb2a","fromNode":"630f2a5feaf2fb22","fromSide":"bottom","toNode":"a0eb3ee9cbb2cdd3","toSide":"top"},
+		{"id":"1bbb0af8fcb604ad","fromNode":"ae7731c5dabfb8ce","fromSide":"bottom","toNode":"e135c0917ca5d3a8","toSide":"top"},
+		{"id":"96ad533a3d4601a6","fromNode":"110e3e478c6c326c","fromSide":"bottom","toNode":"f2682c67d9b9edff","toSide":"top"},
+		{"id":"09aa3f8d7e40bc35","fromNode":"b6fab004d256f8de","fromSide":"left","toNode":"3e2434525fcc8541","toSide":"right"},
+		{"id":"ac47d6e396332dc5","fromNode":"3d7dedce274a492e","fromSide":"left","toNode":"ae9da3db023837af","toSide":"top"},
+		{"id":"94464c9d19a4d5a4","fromNode":"3d7dedce274a492e","fromSide":"left","toNode":"11cab3f937d7e1eb","toSide":"top"}
+	]
+}

docs/Glossary.md

@@ -4,9 +4,9 @@ nav_order: 2
 layout: default
 ---
 
- - Block Diagram Protocol Schema: This schema is used to validate the JSON file that is used to store the block diagram protocol. There are two components, a toolbox which describes the abstract blocks and spaces and the model which has the actual instances of the toolbox - processors, wires and systems.
-   - Toolbox Schema: This schema is used for describing a toolbox in bdp-lib.
-     - Spaces: A list of spaces in the block diagram protocol that follow the space schema. It defines the abstract classes of blocks and spaces which models will instantiate.
+ - Project: A project within the block diagram protocol. The toolbox contains the abstract representations and the workbench contains the implementations.
+   - Toolbox: The abstract classes of blocks and spaces which the workbench will instantiate.
+     - Spaces: A list of spaces in the block diagram protocol that follow the space schema. One can think of a space as a typed dictionary of data.
        - ID: The unique identifier of the space.
        - Name: The name of the space.
        - Description: The description of the space.
@@ -16,14 +16,17 @@ layout: default
        - Description: A description of the block.
        - Domain: The domain of the block which are IDs of spaces. Spaces may be repeated or it may be an empty array.
        - Codomain: The codomain of the block which are IDs of spaces. Spaces may be repeated or it may be an empty array.
-   - Model Schema: This schema is used to describe a model in bdp-lib which is the actual instances of the toolbox which it would be paired with in the large bdp schema.
+   - Workbench: The actual instances in bdp-lib which is the actual instances of the toolbox which it would be paired with in the large bdp project.
      - Processors: A list of processors in the block diagram protocol that follow the processor schema.
        - ID: A unique identifier for the processor.
        - Name: The name of the processor.
        - Description: A description of the processor.
        - Parent: The ID of the block that the processor is an instance of.
        - Ports: The IDs of spaces which must match the domain of the parent block.
        - Terminals: The IDs of spaces which must match the codomain of the parent block.
+       - Subsystem: The subsystem of the processor which is a system that the processor represents and passes its ports to and receives spaces to its terminals from.
+         - System ID: The ID of the system that the processor is a processor for.
+         - Wires: The IDs of the wires that connect the processor ports and terminals to the system ports and terminals.
      - Wires: A list of wires in the block diagram protocol that follow the wire schema.
        - ID: A unique identifier for the wire.
        - Parent: The ID of the space that the wire is passing.

docs/Glossary/Toolbox.md

@@ -0,0 +1,6 @@
+---
+title: Toolbox
+nav_order: 1
+layout: default
+parent: Glossary
+---

docs/Glossary/Toolbox/Block.md

@@ -0,0 +1,6 @@
+---
+title: Block
+nav_order: 1
+layout: default
+parent: Toolbox
+---

docs/Glossary/Toolbox/Space.md

@@ -0,0 +1,6 @@
+---
+title: Space
+nav_order: 2
+layout: default
+parent: Toolbox
+---

docs/Glossary/Workbench.md

@@ -0,0 +1,6 @@
+---
+title: Workbench
+nav_order: 2
+layout: default
+parent: Glossary
+---

docs/Glossary/Workbench/Processor.md

@@ -0,0 +1,6 @@
+---
+title: Processor
+nav_order: 1
+layout: default
+parent: Workbench
+---

docs/Glossary/Workbench/System.md

@@ -0,0 +1,6 @@
+---
+title: System
+nav_order: 3
+layout: default
+parent: Workbench
+---

docs/Glossary/Workbench/Wire.md

@@ -0,0 +1,6 @@
+---
+title: Wire
+nav_order: 2
+layout: default
+parent: Workbench
+---