fixed clock cycle count for lmulu_b and added timings for llmulu_b

Author: ZERICO2005

src/crt/llmulu_b.src

@@ -1,8 +1,15 @@
 	assume	adl=1
 
 	section	.text
+
 	public	__llmulu_b
+
 __llmulu_b:
+; Multiplies BC:UDE:UHL by (SP) and returns the 64-bit unsigned product bc:ude:uhl.
+;    I: (SP) = 8-bit multiplier, BC:UDE:UHL = multiplicand, ADL=1
+;    O: bc:ude:uhl = BC:UDE:UHL * (SP)
+;   CC: 135*r(PC)+21*r(SPL)+18*w(SPL)+33
+;   CC: 134 bytes | 135F + 21R + 18W + 33
 	push	af
 	push	iy
 	ld	iy, 0

src/crt/lmulu_b.src

@@ -9,8 +9,8 @@ __lmulu_b:
 ; Multiplies EUHL by A and returns the 32-bit product euhl.
 ;    I: A=multiplier, EUHL=multiplicand, ADL=1
 ;    O: euhl=EUHL*A
-;   CC: 43*r(PC)+12*r(SPL)+9*w(SPL)+13
-;   CC: 42 bytes | 43F + 12R + 9W + 13
+;   CC: 43*r(PC)+12*r(SPL)+9*w(SPL)+17
+;   CC: 42 bytes | 43F + 12R + 9W + 17
 Mul_EUHL_A_EUHL:
 	push	bc
 	push	de
@@ -45,7 +45,7 @@ Mul_EUHL_A_EUHL:
 	add	hl, hl
 	add	hl, hl
 	add	hl, hl
-	
+
 	mlt	de	; DE = A * L
 	add	hl, de	; UHL = AH.hi + AU.lo, AH.lo + AL.hi, AL.lo
 

src/crt/lmulu_b_fast.src

@@ -9,8 +9,8 @@ __lmulu_b_fast:
 ; Multiplies EUHL by A and returns the 32-bit product euhl.
 ;    I: A=multiplier, EUHL=multiplicand, ADL=1
 ;    O: euhl=EUHL*A
-;   CC: 37*r(PC)+6*r(SPL)+3*w(SPL)+13
-;   CC: 36 bytes | 37F + 6R + 3W + 13
+;   CC: 37*r(PC)+6*r(SPL)+3*w(SPL)+17
+;   CC: 36 bytes | 37F + 6R + 3W + 17
 Mul_EUHL_A_EUHL:
 	dec	sp
 	push	hl
@@ -42,7 +42,7 @@ Mul_EUHL_A_EUHL:
 	add	hl, hl
 	add	hl, hl
 	add	hl, hl
-	
+
 	mlt	de	; DE = A * L
 	add	hl, de	; UHL = AH.hi + AU.lo, AH.lo + AL.hi, AL.lo