Verilog Design Parsing Failed: reg not found.

[nilotpolas]

I'm getting the following error while running a verilog code in SILVER:

/Desktop/Work/FVMaskTools/SILVER-master$ ./bin/verify --verilog=1
[     0.000] Parsing verilog design vlog/mytests/netlist/synth.v with top module top
The target module reg[1:0] not found
cell type or module reg[1:0] not found
Verilog design parsing failed.

The file contains a netlist created from RTL using Yosys. Thanks.