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new file mode 100644
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diff --git a/Report.pdf b/Report.pdf
new file mode 100644
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diff --git a/multiplexer.v b/multiplexer.v
new file mode 100644
index 0000000..ac7299e
--- /dev/null
+++ b/multiplexer.v
@@ -0,0 +1,30 @@
+module mux32to1by1
+(
+    output out,
+    input[4:0] address,
+    input[31:0] inputs
+);
+
+    assign out=inputs[address];
+
+endmodule
+
+module mux32to1by32
+(
+    output[31:0] out,
+    input[4:0] address,
+    input[(32 * 32) - 1:0] input0
+);
+
+    wire[31:0] mux[31:0];
+
+    genvar i;
+    generate
+    for (i = 0; i < 32; i = i + 1) begin: registers
+        assign mux[i] = input0[32 * (i + 1) - 1:32 * i];
+    end
+    endgenerate
+
+    assign out = mux[address];
+
+endmodule
diff --git a/regfile.t.v b/regfile.t.v
index f13815a..58523a9 100644
--- a/regfile.t.v
+++ b/regfile.t.v
@@ -3,6 +3,8 @@
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
 
+`include "regfile.v"
+
 module hw4testbenchharness();
 
   wire[31:0]	ReadData1;	// Data from first register read
@@ -138,6 +140,61 @@ output reg		Clk
     $display("Test Case 2 Failed");
   end
 
+  // Test Case 3:
+  // Write Enable is broken / ignored.
+  WriteRegister = 5'd2;
+  WriteData = 32'd1;
+  RegWrite = 0;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == 1) || (ReadData2 == 1)) begin
+      dutpassed = 0;
+      $display("Test Case 3 Failed");
+  end
+
+  // Test Case 4:
+  // Decoder is broken.
+  WriteRegister = 5'd2;
+  WriteData = 32'd1;
+  RegWrite = 1;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd3;
+
+  #5 Clk=1; #5 Clk=0;
+  if((ReadData1 != 1) || (ReadData2 == 1)) begin
+      dutpassed = 0;
+      $display("Test Case 4 Failed");
+  end
+
+  // Test Case 5:
+  // Register Zero is actually a register.
+  WriteRegister = 5'd0;
+  WriteData = 32'd1;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+
+  #5 Clk=1; #5 Clk=0;
+  if (ReadData1 != 0) begin
+      dutpassed = 0;
+      $display("Test Case 5 Failed");
+  end
+
+  // Test Case 6:
+  // Port 2 is broken and always reads register 14.
+  WriteRegister = 5'd2;
+  WriteData = 32'd1;
+  RegWrite = 1;
+  #5 Clk=1; #5 Clk=0;
+  ReadRegister1 = 5'd2;
+
+  #5 Clk=1; #5 Clk=0;
+  if (ReadData1 != 1) begin
+      dutpassed = 0;
+      $display("Test Case 6 Failed");
+  end
 
   // All done!  Wait a moment and signal test completion.
   #5
@@ -145,4 +202,4 @@ output reg		Clk
 
 end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/regfile.v b/regfile.v
index b8a3c74..4156b7d 100644
--- a/regfile.v
+++ b/regfile.v
@@ -6,6 +6,10 @@
 //   1 synchronous, positive edge triggered write port
 //------------------------------------------------------------------------------
 
+`include "decoders.v"
+`include "multiplexer.v"
+`include "register.v"
+
 module regfile
 (
 output[31:0]	ReadData1,	// Contents of first register read
@@ -21,7 +25,23 @@ input		Clk		// Clock (Positive Edge Triggered)
   // These two lines are clearly wrong.  They are included to showcase how the 
   // test harness works. Delete them after you understand the testing process, 
   // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+  //assign ReadData1 = 42;
+  //assign ReadData2 = 42;
+
+  wire[31:0] writeFinal;
+  wire[(32*32) - 1:0] registerFinal;
+
+  decoder1to32 decoder(writeFinal, RegWrite, WriteRegister);
+  register32zero register1(registerFinal[31:0], WriteData, writeFinal[0], Clk);
+
+  genvar i;
+  generate 
+  for (i = 1; i < 32; i = i + 1) begin: allRegisters
+        register32 register2(registerFinal[32 * (i + 1) - 1:32 * i], WriteData, writeFinal[i], Clk);
+  end
+  endgenerate
+    
+  mux32to1by32 mux1(ReadData1, ReadRegister1, registerFinal);
+  mux32to1by32 mux2(ReadData2, ReadRegister2, registerFinal);
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/register.v b/register.v
index dc9b8cb..6961be0 100644
--- a/register.v
+++ b/register.v
@@ -14,4 +14,36 @@ input		clk
         end
     end
 
+endmodule
+
+module register32
+(
+output reg [31:0] q,
+input [31:0] d,
+input wrenable,
+input clk
+);
+
+    always @(posedge clk) begin
+        if(wrenable) begin
+            q[31:0] = d[31:0];
+        end
+    end
+
+endmodule
+
+module register32zero
+(
+output reg [31:0] q,
+input [31:0] d,
+input wrenable,
+input clk
+);
+
+    always @(posedge clk) begin
+        if(wrenable) begin
+            q[31:0] = 32'b0;
+        end
+    end
+
 endmodule
\ No newline at end of file