diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..318dd74
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+*.out
+*~
diff --git a/decoders.v b/decoders.v
index dd467c2..bd759c9 100644
--- a/decoders.v
+++ b/decoders.v
@@ -1,14 +1,14 @@
 // 32 bit decoder with enable signal
 //   enable=0: all output bits are 0
 //   enable=1: out[address] is 1, all other outputs are 0
+/* Verilator lint_off WIDTH */
 module decoder1to32
 (
-output[31:0]	out,
-input		enable,
-input[4:0]	address
+output[31:0] out,
+input	enable,
+input[4:0] address
 );
 
-    assign out = enable<<address; 
+  assign out = enable<<address;
 
 endmodule
-
diff --git a/deliverable_6.txt b/deliverable_6.txt
new file mode 100644
index 0000000..a413992
--- /dev/null
+++ b/deliverable_6.txt
@@ -0,0 +1 @@
+The module takes as input an enable bit and a 5-bit address, which serves as the "index" variable into the 32 bit array of output wires. When the enable bit is low, all lines are low. When the enable bit is high, the left-shift operator will move the single high value to the indexed position in the 32-bit array. (The 1 starts at position 0, so when the address, or index, is 0, it does not move; if the address is N the 1 is moved "left" by N positions)
diff --git a/hw4_deliverable1.jpg b/hw4_deliverable1.jpg
new file mode 100644
index 0000000..d327fa7
Binary files /dev/null and b/hw4_deliverable1.jpg differ
diff --git a/mux32to1by1.v b/mux32to1by1.v
new file mode 100644
index 0000000..a252e39
--- /dev/null
+++ b/mux32to1by1.v
@@ -0,0 +1,12 @@
+// 32 single-bit inputs multiplexed to 1 single-bit output
+
+module mux32to1by1
+(
+output      out,
+input[4:0]  address,
+input[31:0] inputs
+);
+
+  assign out = inputs[address];
+
+endmodule
diff --git a/mux32to1by32.v b/mux32to1by32.v
new file mode 100644
index 0000000..073a5c1
--- /dev/null
+++ b/mux32to1by32.v
@@ -0,0 +1,47 @@
+// 32 32-bit inputs multiplexed to 1 32-bit output
+
+module mux32to1by32
+(
+output[31:0]  out,
+input[4:0]    address,
+input[31:0]   input0, input1, input2, input3, input4, input5, input6, input7,
+  input8, input9, input10, input11, input12, input13, input14, input15, input16,
+  input17, input18, input19, input20, input21, input22, input23, input24, input25,
+  input26, input27, input28, input29, input30, input31
+);
+
+  wire[31:0] mux[31:0];			// Create a 2D array of wires
+  assign mux[0] = input0;		// Connect the sources of the array
+  assign mux[1] = input1;
+  assign mux[2] = input2;
+  assign mux[3] = input3;
+  assign mux[4] = input4;
+  assign mux[5] = input5;
+  assign mux[6] = input6;
+  assign mux[7] = input7;
+  assign mux[8] = input8;
+  assign mux[9] = input9;
+  assign mux[10] = input10;
+  assign mux[11] = input11;
+  assign mux[12] = input12;
+  assign mux[13] = input13;
+  assign mux[14] = input14;
+  assign mux[15] = input15;
+  assign mux[16] = input16;
+  assign mux[17] = input17;
+  assign mux[18] = input18;
+  assign mux[19] = input19;
+  assign mux[20] = input20;
+  assign mux[21] = input21;
+  assign mux[22] = input22;
+  assign mux[23] = input23;
+  assign mux[24] = input24;
+  assign mux[25] = input25;
+  assign mux[26] = input26;
+  assign mux[27] = input27;
+  assign mux[28] = input28;
+  assign mux[29] = input29;
+  assign mux[30] = input30;
+  assign mux[31] = input31;
+  assign out = mux[address];	// Connect the output of the array
+endmodule
diff --git a/regfile.t.v b/regfile.t.v
index f13815a..fa75243 100644
--- a/regfile.t.v
+++ b/regfile.t.v
@@ -1,21 +1,24 @@
 //------------------------------------------------------------------------------
-// Test harness validates hw4testbench by connecting it to various functional 
+// Test harness validates hw4testbench by connecting it to various functional
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
 
+`include "regfile.v"
+
 module hw4testbenchharness();
 
-  wire[31:0]	ReadData1;	// Data from first register read
-  wire[31:0]	ReadData2;	// Data from second register read
-  wire[31:0]	WriteData;	// Data to write to register
+  wire[31:0] ReadData1;	// Data from first register read
+  wire[31:0] ReadData2;	// Data from second register read
+  wire[31:0] WriteData;	// Data to write to register
   wire[4:0]	ReadRegister1;	// Address of first register to read
   wire[4:0]	ReadRegister2;	// Address of second register to read
   wire[4:0]	WriteRegister;  // Address of register to write
-  wire		RegWrite;	// Enable writing of register when High
-  wire		Clk;		// Clock (Positive Edge Triggered)
+  wire RegWrite;	// Enable writing of register when High
+  wire Clk;		// Clock (Positive Edge Triggered)
 
-  reg		begintest;	// Set High to begin testing register file
-  wire		dutpassed;	// Indicates whether register file passed tests
+  reg begintest;	// Set High to begin testing register file
+  wire endtest;   // Indicates when testing is over
+  wire dutpassed;	// Indicates whether register file passed tests
 
   // Instantiate the register file being tested.  DUT = Device Under Test
   regfile DUT
@@ -34,15 +37,15 @@ module hw4testbenchharness();
   hw4testbench tester
   (
     .begintest(begintest),
-    .endtest(endtest), 
+    .endtest(endtest),
     .dutpassed(dutpassed),
     .ReadData1(ReadData1),
     .ReadData2(ReadData2),
-    .WriteData(WriteData), 
-    .ReadRegister1(ReadRegister1), 
+    .WriteData(WriteData),
+    .ReadRegister1(ReadRegister1),
     .ReadRegister2(ReadRegister2),
     .WriteRegister(WriteRegister),
-    .RegWrite(RegWrite), 
+    .RegWrite(RegWrite),
     .Clk(Clk)
   );
 
@@ -107,7 +110,7 @@ output reg		Clk
     dutpassed = 1;
     #10
 
-  // Test Case 1: 
+  // Test Case 1:
   //   Write '42' to register 2, verify with Read Ports 1 and 2
   //   (Passes because example register file is hardwired to return 42)
   WriteRegister = 5'd2;
@@ -116,6 +119,8 @@ output reg		Clk
   ReadRegister1 = 5'd2;
   ReadRegister2 = 5'd2;
   #5 Clk=1; #5 Clk=0;	// Generate single clock pulse
+  $display("Written: %d Write: %d Read: %d %d Read1: %d Read2: %d", WriteData,
+    WriteRegister, ReadRegister1, ReadRegister2, ReadData1, ReadData2);
 
   // Verify expectations and report test result
   if((ReadData1 != 42) || (ReadData2 != 42)) begin
@@ -123,7 +128,7 @@ output reg		Clk
     $display("Test Case 1 Failed");
   end
 
-  // Test Case 2: 
+  // Test Case 2:
   //   Write '15' to register 2, verify with Read Ports 1 and 2
   //   (Fails with example register file, but should pass with yours)
   WriteRegister = 5'd2;
@@ -132,12 +137,126 @@ output reg		Clk
   ReadRegister1 = 5'd2;
   ReadRegister2 = 5'd2;
   #5 Clk=1; #5 Clk=0;
+  $display("Written: %d Write: %d Read: %d %d Read1: %d Read2: %d", WriteData,
+    WriteRegister, ReadRegister1, ReadRegister2, ReadData1, ReadData2);
 
   if((ReadData1 != 15) || (ReadData2 != 15)) begin
     dutpassed = 0;
     $display("Test Case 2 Failed");
   end
 
+  // Test Case 3:
+  //   Write '1432' to register 23, verify with Read Ports 1 and 2
+  WriteRegister = 5'd23;
+  WriteData = 32'd1432;
+  RegWrite = 1;
+  ReadRegister1 = 5'd23;
+  ReadRegister2 = 5'd23;
+  #5 Clk=1; #5 Clk=0;
+  $display("Written: %d Write: %d Read: %d %d Read1: %d Read2: %d", WriteData,
+    WriteRegister, ReadRegister1, ReadRegister2, ReadData1, ReadData2);
+
+  if((ReadData1 != 1432) || (ReadData2 != 1432)) begin
+    dutpassed = 0;
+    $display("Test Case 3 Failed");
+  end
+
+  // Test Case 4:
+  //   Write '33' to register 23 without Write Enable, verify read is same as previous
+  WriteRegister = 5'd23;
+  WriteData = 32'd33;
+  RegWrite = 0;
+  ReadRegister1 = 5'd23;
+  ReadRegister2 = 5'd23;
+  #5 Clk=1; #5 Clk=0;
+  $display("Written: %d Write: %d Read: %d %d Read1: %d Read2: %d", WriteData,
+    WriteRegister, ReadRegister1, ReadRegister2, ReadData1, ReadData2);
+
+  if((ReadData1 != 1432) || (ReadData2 != 1432)) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed");
+  end
+
+  // Test Case 5:
+  //   Write '33' to register 23, verify register 2 is not written to
+  WriteRegister = 5'd23;
+  WriteData = 32'd33;
+  RegWrite = 1;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+  $display("Written: %d Write: %d Read: %d %d Read1: %d Read2: %d", WriteData,
+    WriteRegister, ReadRegister1, ReadRegister2, ReadData1, ReadData2);
+
+  if((ReadData1 != 15) || (ReadData2 != 15)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+  // Test Case 6:
+  //   Write '33' to register 0, verify still returns 0
+  WriteRegister = 5'd0;
+  WriteData = 32'd33;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd0;
+  #5 Clk=1; #5 Clk=0;
+  $display("Written: %d Write: %d Read: %d %d Read1: %d Read2: %d", WriteData,
+    WriteRegister, ReadRegister1, ReadRegister2, ReadData1, ReadData2);
+
+  if((ReadData1 != 0) || (ReadData2 != 0)) begin
+    dutpassed = 0;
+    $display("Test Case 6 Failed");
+  end
+
+  // Test Case 7:
+  //   Write '1432' to register 31, verify read
+  WriteRegister = 5'd31;
+  WriteData = 32'd1432;
+  RegWrite = 1;
+  ReadRegister1 = 5'd31;
+  ReadRegister2 = 5'd31;
+  #5 Clk=1; #5 Clk=0;
+  $display("Written: %d Write: %d Read: %d %d Read1: %d Read2: %d", WriteData,
+    WriteRegister, ReadRegister1, ReadRegister2, ReadData1, ReadData2);
+
+  if((ReadData1 != 1432) || (ReadData2 != 1432)) begin
+    dutpassed = 0;
+    $display("Test Case 7 Failed");
+  end
+
+  // Test Case 8:
+  //   Write '2543' to register 30, verify read registers operate independently
+  WriteRegister = 5'd30;
+  WriteData = 32'd2543;
+  RegWrite = 1;
+  ReadRegister1 = 5'd30;
+  ReadRegister2 = 5'd31;
+  #5 Clk=1; #5 Clk=0;
+  $display("Written: %d Write: %d Read: %d %d Read1: %d Read2: %d", WriteData,
+    WriteRegister, ReadRegister1, ReadRegister2, ReadData1, ReadData2);
+
+  if((ReadData1 != 2543) || (ReadData2 != 1432)) begin
+    dutpassed = 0;
+    $display("Test Case 8 Failed");
+  end
+
+  // Test Case 9:
+  //   Same as above, but flipped and different registers
+  WriteRegister = 5'd1;
+  WriteData = 32'd2543;
+  RegWrite = 1;
+  ReadRegister1 = 5'd23;
+  ReadRegister2 = 5'd1;
+  #5 Clk=1; #5 Clk=0;
+  $display("Written: %d Write: %d Read: %d %d Read1: %d Read2: %d", WriteData,
+    WriteRegister, ReadRegister1, ReadRegister2, ReadData1, ReadData2);
+
+  if((ReadData1 != 33) || (ReadData2 != 2543)) begin
+    dutpassed = 0;
+    $display("Test Case 9 Failed");
+  end
+
 
   // All done!  Wait a moment and signal test completion.
   #5
@@ -145,4 +264,4 @@ output reg		Clk
 
 end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/regfile.v b/regfile.v
index b8a3c74..019f20f 100644
--- a/regfile.v
+++ b/regfile.v
@@ -6,22 +6,48 @@
 //   1 synchronous, positive edge triggered write port
 //------------------------------------------------------------------------------
 
+`include "register32.v"
+`include "register32zero.v"
+`include "decoders.v"
+`include "mux32to1by32.v"
+
 module regfile
 (
-output[31:0]	ReadData1,	// Contents of first register read
-output[31:0]	ReadData2,	// Contents of second register read
-input[31:0]	WriteData,	// Contents to write to register
-input[4:0]	ReadRegister1,	// Address of first register to read
-input[4:0]	ReadRegister2,	// Address of second register to read
-input[4:0]	WriteRegister,	// Address of register to write
-input		RegWrite,	// Enable writing of register when High
-input		Clk		// Clock (Positive Edge Triggered)
+output[31:0] ReadData1,	// Contents of first register read
+output[31:0] ReadData2,	// Contents of second register read
+input[31:0] WriteData,	// Contents to write to register
+input[4:0] ReadRegister1,	// Address of first register to read
+input[4:0] ReadRegister2,	// Address of second register to read
+input[4:0] WriteRegister,	// Address of register to write
+input	RegWrite,	// Enable writing of register when High
+input	Clk		// Clock (Positive Edge Triggered)
 );
 
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+wire[31:0] regOut[31:0];
+wire[31:0] regEnable;
+genvar i;
+
+  decoder1to32 decoder(regEnable, RegWrite, WriteRegister);
+
+  register32zero register0 (regOut[0], WriteData, regEnable[0], Clk);
+  generate
+  for (i = 1; i < 32; i = i+1) begin : register_generate
+    register32 register (regOut[i], WriteData, regEnable[i], Clk);
+  end
+  endgenerate
+
+  mux32to1by32 multiplexer1 (ReadData1, ReadRegister1, regOut[0], regOut[1],
+    regOut[2], regOut[3], regOut[4], regOut[5], regOut[6], regOut[7], regOut[8],
+    regOut[9], regOut[10], regOut[11], regOut[12], regOut[13], regOut[14],
+    regOut[15], regOut[16], regOut[17], regOut[18], regOut[19], regOut[20],
+    regOut[21], regOut[22], regOut[23], regOut[24], regOut[25], regOut[26],
+    regOut[27], regOut[28], regOut[29], regOut[30], regOut[31]);
+
+  mux32to1by32 multiplexer2 (ReadData2, ReadRegister2, regOut[0], regOut[1],
+    regOut[2], regOut[3], regOut[4], regOut[5], regOut[6], regOut[7], regOut[8],
+    regOut[9], regOut[10], regOut[11], regOut[12], regOut[13], regOut[14],
+    regOut[15], regOut[16], regOut[17], regOut[18], regOut[19], regOut[20],
+    regOut[21], regOut[22], regOut[23], regOut[24], regOut[25], regOut[26],
+    regOut[27], regOut[28], regOut[29], regOut[30], regOut[31]);
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/register.v b/register.v
index dc9b8cb..61839a5 100644
--- a/register.v
+++ b/register.v
@@ -2,16 +2,16 @@
 //   Positive edge triggered
 module register
 (
-output reg	q,
-input		d,
-input		wrenable,
-input		clk
+output reg q,
+input d,
+input wrenable,
+input	clk
 );
 
-    always @(posedge clk) begin
-        if(wrenable) begin
-            q = d;
-        end
+  always @(posedge clk) begin
+    if(wrenable) begin
+      q = d;
     end
+  end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/register32.v b/register32.v
new file mode 100644
index 0000000..45e45d0
--- /dev/null
+++ b/register32.v
@@ -0,0 +1,18 @@
+// 32-bit D Flip-Flop with enable
+//   Positive edge triggered
+
+module register32
+(
+output reg[31:0] q,
+input[31:0] d,
+input wrenable,
+input	clk
+);
+
+  always @(posedge clk) begin
+    if(wrenable) begin
+      q = d;
+    end
+  end
+
+endmodule
diff --git a/register32zero.v b/register32zero.v
new file mode 100644
index 0000000..0b43023
--- /dev/null
+++ b/register32zero.v
@@ -0,0 +1,16 @@
+// 32-bit D Flip-Flop with enable
+//   Positive edge triggered
+
+module register32zero
+(
+output reg[31:0] q,
+input[31:0] d,
+input wrenable,
+input	clk
+);
+
+  always @(posedge clk) begin
+    q = 32'b0;
+  end
+
+endmodule