pistachio: add watchdog support

Change-Id: I5859d15e6c114734f1813d1e67d86aed587cdb63
Signed-off-by: Avinash Tahakik <[email protected]>

Author: Avinash95

board/imgtec/pistachio_bub/clocks.c

@@ -128,6 +128,11 @@
 #define USB_TIMEOUT_VALUE_US		200000
 #define SYS_CLK_LOCK_DELAY		3
 
+/* Definitions for Watchdog setup */
+#define WDCLKDIV1_CTRL_ADDR		(0x18144800 + 0x0124)
+#define WDCLKDIV1_MASK			0x0000007F
+#define WDCLKOUT_CTRL_ADDR		(0x18144800 + 0x0128)
+#define WDCLKOUT_MASK			0x0000007F
 
 #ifdef CONFIG_SPL_BUILD
 struct pll_parameters {
@@ -517,4 +522,32 @@ void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface)
 	reg |= divider2 & I2CCLKOUT_MASK;
 	writel(reg, I2CCLKOUT_CTRL_ADDR(interface));
 }
+
+/*
+ * wd_clk_setup: sets up clocks for pistachio watchdog
+ * divider1: 7-bit divider value
+ * divider2: 7-bit divider value
+ */
+#ifdef CONFIG_PISTACHIO_WATCHDOG
+void wd_clk_setup(u8 divider1, u16 divider2)
+{
+	u32 reg;
+
+	/* Check input parameters */
+	assert(!(divider1 & ~(WDCLKDIV1_MASK)));
+	assert(!(divider2 & ~(WDCLKOUT_MASK)));
+
+	/* Set divider 1 */
+	reg = readl(WDCLKDIV1_CTRL_ADDR);
+	reg &= ~WDCLKDIV1_MASK;
+	reg |= divider1 & WDCLKDIV1_MASK;
+	writel(reg, WDCLKDIV1_CTRL_ADDR);
+
+	/* Set divider 2 */
+	reg = readl(WDCLKOUT_CTRL_ADDR);
+	reg &= ~WDCLKOUT_MASK;
+	reg |= divider2 & WDCLKOUT_MASK;
+	writel(reg, WDCLKOUT_CTRL_ADDR);
+}
+#endif /*CONFIG_PISTACHIO_WATCHDOG*/
 #endif

board/imgtec/pistachio_bub/clocks.h

@@ -25,6 +25,9 @@ int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel);
 void rom_clk_setup(u8 divider);
 void eth_clk_setup(u8 mux, u8 divider);
 void setup_clk_gate_defaults(void);
+#ifdef CONFIG_PISTACHIO_WATCHDOG
+void wd_clk_setup(u8 divider1, u16 divider2);
+#endif /*CONFIG_PISTACHIO_WATCHDOG*/
 
 enum {
 	CLOCKS_OK = 0,

board/imgtec/pistachio_bub/pistachio.c

@@ -19,6 +19,7 @@
 #include <asm/mipsregs.h>
 #include <asm/pistachio.h>
 #include <asm-generic/sections.h>
+#include <watchdog.h>
 
 #include "mfio.h"
 
@@ -169,6 +170,14 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+#ifdef CONFIG_PISTACHIO_WATCHDOG
+	hw_watchdog_init();
+#endif
+	return 0;
+}
+
 int misc_init_r(void)
 {
 	return 0;

board/imgtec/pistachio_bub/spl_pistachio.c

@@ -11,7 +11,6 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <spl.h>
-
 #include "clocks.h"
 #include "ddr_init.h"
 #include "mfio.h"
@@ -78,6 +77,9 @@ void spl_lowlevel_init(void) {
 	eth_clk_setup(0, 6);
 	rom_clk_setup(1);
 	usb_clk_setup(6, 2, 7);
+#ifdef CONFIG_PISTACHIO_WATCHDOG
+	wd_clk_setup(87, 120);
+#endif
 #if defined(CONFIG_TARGET_PISTACHIO_MARDUK) || \
 	defined(CONFIG_TARGET_PISTACHIO_BEETLE)
 	mfio_setup_usb_pwr();

doc/README.watchdog

@@ -33,3 +33,15 @@ CONFIG_XILINX_TB_WATCHDOG
 
 CONFIG_BFIN_WATCHDOG
 	Available for bf5xx and bf6xx to service the watchdog.
+
+CONFIG_PISTACHIO_WATCHDOG
+	Available for pistachio to service the watchdog.
+	one needs to define following configs to have full watchdog support
+	CONFIG_HW_WATCHDOG
+	CONFIG_PISTACHIO_WATCHDOG
+	CONFIG_SPL_WATCHDOG_SUPPORT
+	CONFIG_BOARD_LATE_INIT
+
+CONFIG_PISTACHIO_WATCHDOG_TIMEOUT_SEC
+	Can be used to change the timeout for pistachio watchdog.
+	Actual timeout may vary please check comment header in drivers/watchdog/pistachio_wdt.c

drivers/watchdog/Makefile

@@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
 obj-$(CONFIG_BFIN_WATCHDOG)  += bfin_wdt.o
 obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
 obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_PISTACHIO_WATCHDOG) += pistachio_wdt.o

drivers/watchdog/pistachio_wdt.c

@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Avinash Tahakik <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Notes
+ * -----
+ * The timeout value is rounded to the next power of two clock cycles.
+ * This is configured using the PDC_WDT_CONFIG register, according to this
+ * formula:
+ *
+ *     timeout = 2^(delay + 1) clock cycles
+ *
+ * Where 'delay' is the value written in PDC_WDT_CONFIG register.
+ *
+ * Therefore, the hardware only allows to program watchdog timeouts, expressed
+ * as a power of two number of watchdog clock cycles. The current implementation
+ * guarantees that the actual watchdog timeout will be _at least_ the value
+ * programmed in the imgpdg_wdt driver.
+ *
+ * The following table shows how the user-configured timeout relates
+ * to the actual hardware timeout (watchdog clock @ 40000 Hz):
+ *
+ * input timeout | WD_DELAY | actual timeout
+ * -----------------------------------
+ *      10       |   18     |  13 seconds
+ *      20       |   19     |  26 seconds
+ *      30       |   20     |  52 seconds
+ *      60       |   21     |  104 seconds
+ *
+ * Albeit coarse, this granularity would suffice most watchdog uses.
+ * If the platform allows it, the user should be able to change the watchdog
+ * clock rate and achieve a finer timeout granularity.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <linux/log2.h>
+
+/* registers */
+
+#define PDC_WDT_BASE				0x18102100
+#define PDC_WDT_SOFT_RESET			0x00
+#define PDC_WDT_SOFT_RESET_VALUE	0X1
+#define PDC_WDT_CONFIG				0x04
+#define PDC_WDT_CONFIG_ENABLE		(1 << 31)
+#define PDC_WDT_CONFIG_DELAY_MASK	0x1f
+
+#define PDC_WDT_TICKLE1				0x08
+#define PDC_WDT_TICKLE1_MAGIC		0xabcd1234
+#define PDC_WDT_TICKLE2				0x0c
+#define PDC_WDT_TICKLE2_MAGIC		0x4321dcba
+
+#define CLOCK_RATE					32871
+
+#ifndef CONFIG_PISTACHIO_WATCHDOG_TIMEOUT_SEC
+#define CONFIG_PISTACHIO_WATCHDOG_TIMEOUT_SEC 60
+#endif
+
+static void wdt_keepalive(void)
+{
+	writel(PDC_WDT_TICKLE1_MAGIC, PDC_WDT_BASE + PDC_WDT_TICKLE1);
+	writel(PDC_WDT_TICKLE2_MAGIC, PDC_WDT_BASE + PDC_WDT_TICKLE2);
+}
+
+static void wdt_set_timeout(unsigned int timeout)
+{
+	unsigned int val;
+
+	val = readl(PDC_WDT_BASE + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK;
+	val |= order_base_2(timeout * CLOCK_RATE) - 1;
+	writel(val, PDC_WDT_BASE + PDC_WDT_CONFIG);
+}
+
+void hw_watchdog_reset(void)
+{
+	wdt_keepalive();
+}
+
+void hw_watchdog_init(void)
+{
+	unsigned int val;
+
+	wdt_set_timeout(CONFIG_PISTACHIO_WATCHDOG_TIMEOUT_SEC);
+
+	val = readl(PDC_WDT_BASE + PDC_WDT_CONFIG);
+	val |= PDC_WDT_CONFIG_ENABLE;
+	writel(val, PDC_WDT_BASE + PDC_WDT_CONFIG);
+}