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| 1 | +/* |
| 2 | + * Copyright (C) 2015 Imagination Technologies |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ |
| 5 | + */ |
| 6 | + |
| 7 | +#include <asm/mipsregs.h> |
| 8 | +#include <asm/mmu.h> |
| 9 | + |
| 10 | +#include <linux/kernel.h> |
| 11 | +#include <linux/sizes.h> |
| 12 | + |
| 13 | +#include <common.h> |
| 14 | + |
| 15 | +#define MIN_PAGE_SIZE SZ_4K |
| 16 | + |
| 17 | +static int add_wired_tlb_entry(u32 entrylo0, u32 entrylo1, |
| 18 | + u32 entryhi, u32 pgsize) |
| 19 | +{ |
| 20 | + u32 tlbindex; |
| 21 | + |
| 22 | + tlbindex = read_c0_wired(); |
| 23 | + if (tlbindex >= get_tlb_size() || tlbindex >= C0_WIRED_MASK) { |
| 24 | + return -1; |
| 25 | + } |
| 26 | + write_c0_wired(tlbindex + 1); |
| 27 | + write_c0_index(tlbindex); |
| 28 | + write_c0_pagemask(((pgsize / MIN_PAGE_SIZE) - 1) << C0_PAGEMASK_SHIFT); |
| 29 | + write_c0_entryhi(entryhi); |
| 30 | + write_c0_entrylo0(entrylo0); |
| 31 | + write_c0_entrylo1(entrylo1); |
| 32 | + mtc0_tlbw_hazard(); |
| 33 | + tlb_write_indexed(); |
| 34 | + tlbw_use_hazard(); |
| 35 | + |
| 36 | + return 0; |
| 37 | +} |
| 38 | + |
| 39 | +static u32 pick_pagesize(u32 start, u32 len) |
| 40 | +{ |
| 41 | + u32 pgsize, max_pgsize; |
| 42 | + |
| 43 | + max_pgsize = get_max_pagesize(); |
| 44 | + for (pgsize = max_pgsize; |
| 45 | + pgsize >= MIN_PAGE_SIZE; |
| 46 | + pgsize = pgsize / 4) { |
| 47 | + /* |
| 48 | + * Each TLB entry maps a pair of virtual pages. To avoid |
| 49 | + * aliasing, pick the largest page size that is at most |
| 50 | + * half the size of the region we're trying to map. |
| 51 | + */ |
| 52 | + if (IS_ALIGNED(start, 2 * pgsize) && (2 * pgsize <= len)) |
| 53 | + break; |
| 54 | + } |
| 55 | + |
| 56 | + return pgsize; |
| 57 | +} |
| 58 | + |
| 59 | +/* |
| 60 | + * Identity map the memory from [start,start+len] in the TLB using the |
| 61 | + * largest suitable page size so as to conserve TLB entries. |
| 62 | + */ |
| 63 | +int identity_map(u32 start, size_t len, u32 coherency) |
| 64 | +{ |
| 65 | + u32 pgsize, pfn, entryhi, entrylo0, entrylo1; |
| 66 | + |
| 67 | + coherency &= C0_ENTRYLO_COHERENCY_MASK; |
| 68 | + while (len > 0) { |
| 69 | + pgsize = pick_pagesize(start, len); |
| 70 | + entryhi = start; |
| 71 | + pfn = start >> 12; |
| 72 | + entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | coherency | |
| 73 | + C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G; |
| 74 | + start += pgsize; |
| 75 | + len -= min(len, pgsize); |
| 76 | + if (len >= pgsize) { |
| 77 | + pfn = start >> 12; |
| 78 | + entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) | |
| 79 | + coherency | C0_ENTRYLO_D | C0_ENTRYLO_V | |
| 80 | + C0_ENTRYLO_G; |
| 81 | + start += pgsize; |
| 82 | + len -= min(len, pgsize); |
| 83 | + } else { |
| 84 | + entrylo1 = 0; |
| 85 | + } |
| 86 | + if (add_wired_tlb_entry(entrylo0, entrylo1, entryhi, pgsize)) |
| 87 | + return -1; |
| 88 | + } |
| 89 | + |
| 90 | + return 0; |
| 91 | +} |
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