From 4bc75d187f30491176a39745c902bdab0cb89a37 Mon Sep 17 00:00:00 2001
From: Derek Henderson <62639977+D3r3k23@users.noreply.github.com>
Date: Sun, 4 Apr 2021 02:16:48 -0700
Subject: [PATCH] Update README.md

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 72ec088..23ded68 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 
 # clk_divider demo
 
-In the testbench, a 1 kHz (1 ms period) clock is generated for clk_in. The DIV parameter for the clk_divider module is set to 10, to divide the frequency of clk_in by 10 and produce a clk_out of 100 Hz. In clk_divider, a DIV of 10 means that TC (terminal count) is 4. So when count is 4, terminate is activated, and clk_out is inverted. The simulation waveform shows that clk_out has a period of 10 ms, so a frequency of 100 Hz. It has a rising edge once every 10 cycles on clk_in.
+In the testbench, a 1 kHz (1 ms period) clock is generated for clk_in. The DIV parameter for the clk_divider module is set to 10, to divide the frequency of clk_in by 10 and produce a clk_out of 100 Hz. In clk_divider, a DIV of 10 means that TC (terminal count) is 4. So when count is 4, terminate is activated, and clk_out has a rising or falling edge. The simulation waveform shows that clk_out has a period of 10 ms, so a frequency of 100 Hz. It has a rising edge once every 10 cycles on clk_in.
 
 ### clk_divider_tb behavioral simulation
 ![Simulation](./sim.png?raw=true)