From 5d343ae96c1ee880b45983d79d9f2291c2b9ecbb Mon Sep 17 00:00:00 2001
From: Derek Henderson <62639977+D3r3k23@users.noreply.github.com>
Date: Tue, 20 Apr 2021 02:45:43 -0700
Subject: [PATCH] Update clk_divider_tb.v

---
 clk_divider_tb.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clk_divider_tb.v b/clk_divider_tb.v
index c4ce362..ce63fc9 100644
--- a/clk_divider_tb.v
+++ b/clk_divider_tb.v
@@ -12,7 +12,7 @@ module clk_divider_tb;
 
     // 1 kHz clock gen
     initial     clk_in = 1'b0;
-    always #500 clk_in <= ~clk_in; // 1 ms period
+    always #500 clk_in = ~clk_in; // 1 ms period
 
     clk_divider #( .DIV(10) ) DUT // Divide clock frequency by 10
     (