mb/clevo/tgl-u: update dt syntax for usb ports

Change-Id: I433dfcef9d1cf8f34299a16e0478edfbfe5ae717
Signed-off-by: Michał Kopeć <[email protected]>

Author: mkopec

src/mainboard/clevo/tgl-u/variants/ns50mu/devicetree.cb

@@ -100,6 +100,20 @@ chip soc/intel/tigerlake
 		end
 
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP), 		// USB-A daughterboard
+				[1] = USB2_PORT_TYPE_C(OC_SKIP), 	// USB-C mainboard
+				[2] = USB2_PORT_MID(OC_SKIP), 		// USB-A mainboard
+				[4] = USB2_PORT_MID(OC_SKIP), 		// Fingerprint Reader
+				[5] = USB2_PORT_TYPE_C(OC_SKIP), 	// TBT USB-C
+				[6] = USB2_PORT_MID(OC_SKIP),		// CCD
+				[9] = USB2_PORT_MID(OC_SKIP),		// BT
+			}"
+			register "usb3_ports" = "{
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-C port2 (lane 0)
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-A port3
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-C port4 (lane 1)
+			}"
 			# USB2
 			register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" 	# USB-A daughterboard
 			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" 	# USB-C motherboard

src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb

@@ -100,20 +100,21 @@ chip soc/intel/tigerlake
 		end
 
 		device ref south_xhci on
-			# USB2
-			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" 	# USB-A port1
-			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" 	# USB-C port2
-			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" 	# USB-A port3
-			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" 	# Finger
-			register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" 	# TBT USB-C
-			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# CCD
-			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# BT
-			# USB3
-			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A port1
-			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C port2 (right port, lane 0)
-			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A port3
-			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C port4 (right port, lane 1)
-			# ACPI
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP), 		// USB-A port1
+				[1] = USB2_PORT_TYPE_C(OC_SKIP), 	// USB-C port2
+				[2] = USB2_PORT_MID(OC_SKIP), 		// USB-A port3
+				[4] = USB2_PORT_MID(OC_SKIP), 		// Fingerprint Reader
+				[5] = USB2_PORT_TYPE_C(OC_SKIP), 	// TBT USB-C
+				[6] = USB2_PORT_MID(OC_SKIP),		// CCD
+				[9] = USB2_PORT_MID(OC_SKIP),		// BT
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-A port1
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-C port2 (right port, lane 0)
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-A port3
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-C port4 (right port, lane 1)
+			}"
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi