From e972ef1c64706087e40b44856a6baa7a7507c955 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sat, 26 Oct 2024 13:15:38 +0200 Subject: [PATCH 01/13] mb/lenovo/m900_tiny: Update VBT to build 1037 with Kaby Lake gfx support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update VBT to one extracted from newer Lenovo UEFI, version FWKTBFA. The newer VBT has build number 1037 and supports Kaby Lake graphics, while the old VBT with build number 1000 only supports Skylake. The old VBT starts with $VBT_SKYLAKE while the new one starts with $VBT_KABYLAKE. TEST=Insert CPU with integrated HD 630 graphics (i3-7100) and check if all video outputs work in firmware. Upstream-Status: Backport Change-Id: I5e108d4ad8bf0663f3e1fa32145e40ea9babeac5 Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/coreboot/+/84873 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Matt DeVillier Reviewed-by: Alicja Michalska Signed-off-by: Michał Kopeć --- src/mainboard/lenovo/m900_tiny/data.vbt | Bin 4608 -> 8192 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/m900_tiny/data.vbt b/src/mainboard/lenovo/m900_tiny/data.vbt index 7e6fe3dc1399c6c0793e24ff34cf789f84da426b..4c26ae512bd8fd364796b3f273419252cf18968f 100644 GIT binary patch literal 8192 zcmds54R934m436ov$HGhvPdAyk~{_>3n7+80*uk_vHDvi5YkG5m5@OaL~7#;22Pq4 zrw;6JJ9<05AANEPOUi5V zvR7r-D6Q@K%Gj_<`yb$qe!r498BOL!^_x%v4E zY?%vqetyQhjLdl%_W293{oInw%q0t+i{kR~b4ylw3X8H=6_yn9C1reGVR?3WdH%|r zqBXpytfZhYr*Kt%UKB^qlDlQ=HyU1iVWYsO=Fa9b>~{NHlsBK3w#?^lY1nGxvo~$x z%P3DHUsm5(-_TTFXN%(K{BB@13;?4AeGf2jCj;tSkjz7#3u;}!^Ptgy%k`+v?)6we zwUAM108&`!-9FLJV*|yjB^m`uwNz=KcOzIV?64IiS`VO=MlB4_NDXA>UGVE#%Ee8U zxmW;P0w12?RdNH{yuy{Ba2Wt}(x9E;<)wM#vd}Jz1#AkJ#38-z=epM`uXsN#xA}*< z9;W|NE;Sx^?4KVJO37%(4nNcgVLNbB@RBKy z)g&o;f{gh$(8bGy-Z9bnaQ(kI5>I2olWELFJqH){x0tty+>taX6p?y&q!gLR>S zTWa9z4c2W2uEoIr$Y5sR$L{wdK?nq(VH=(&|DlT_bgELdyJ&tQyv)F_K~GV=8_@#;#|<0Tw2 z^Dw_Mflu|v$T~_|v{NOU!$gC@<0aHR0j_LFvB&LQBuj`}v{Nl-cibjus00UQ+&_H^ zdm6l63U-%$D`sK(;2v-yZJD-f<0mCyJ6{@aaarz@!0eZ>!z3jfowvQOG(N>u`TD&* zF#9FMU~=h>Pht-ROI`L2$1_~6?t2n+a{e@VwUf~#dD{C{DJ0q5`xRSIP41T>FK%Tr zde~vxf2cM-$z|siTc9R2`w{w}CjI)!oFdiXKeYAuOq7sDXUVqMFJ(E?A?@x-_`~;S zAG%n&dxqWfz3F!)sKH3vsL9Dlu&24s)$Xpd$Cb)?i28#XLkE@cSNfzRAxf5@mYENe}A%cpoKAE|&a(I{BaWYSj{d+&?Xz>#Cf4&lYMhOA>$u-Q(}Y zY!}q}VQQ_#GKJ2P_kckZA5)RrQ{!2`xqege`j_he9}x6V4?c5RK)2lT3{<|g{2b!C zzsWoD(DUF90McXOn{MnZM4Y!8lT{t0Gye*r+IAdZ@7?F`qbZ;5kQTas#lX$i7D9LQ z3}`CRs#(?QV1MAfE5t**q=E#$*z1juv+hqRAJ+Zw+jv@wbWX2(OyBDsRrk6_ntI*C zCB5!Jw%7ef<|Nna9;aM4(PGeAJleW>xYhed^U2$#W#*H;L!SkQiTPAF8Tx(I8j|G} z&9A-+Sob$Trilcn%3P z-vlAqe}-A&9W=kPHsb#|vt;v#`IVB0zlT{;JZ9dN6Y)2XGXfstj{mv}H}nPR`Mu>d zzzL4DH21j>5;tj219L)aKItAB9C#(v#=!UmL361uJZv1!h`b&BQ+?}5_h%~Ai0aOg z=G%=HT*QCJ*z`Fr;U9UTsZSYgt-hW1aqCD+SfvUMkl^ovACRE8FQc2#qg4j~Yh8%7 zs4*L}CLLyVYM_cP2E?A_zBKVTm`{EwUY$00MkOS8yIK-R%Shi06*OsDdUZf-!30~d zNK+lwz5`<7IGWacY7oy6M~uHC)tQ4~b>J6_v`k3nDKGO@taeOoN)(+l#P6hw-3uEn zfqrYS{~bpB_xWN=df+{4I72*iJ52=m|}Rs*WKZZ-r=|Cf3)!!!$U$mL;BEnHcC*5u5p>hLn*G5#uQt zx<;x<*0}~fj${orT(h;Vir`?d2kmg43|+<1;JJ+Mu*$^LppHUk7*cCH{DZ^}0}Nej z=V0gy$_T6-7g-^97a9NILO)ux$&O z@CN7MdvqBSE^}6^m2qf0&V+NEyYA6vm~e)3kwzKUv?Zv*Gn^MEXj9uis=`)ho>mz* zwH;A~RpD{c6;GFb&0{-N>Uwq8Ej{Do0H-oBzo8osTI|+qPNP{y4KmeWzV-W(4hwL=m$p`VWIeGjQ=+4<7|UEeUwU=6@H2iYeC#chiNw##S774R%)?= zMphfDguD9*N6|CQvJ~k^XvYtrXC}V(Xs+S0*p-4G;=rn0NYTenU-;4OR|=q~8mPO< z4;4!V(Znq!Zw(kta{9s^9*YZ0tx}M6!c3(Vr$0(+*MhB8yEr76ZLRqX*80HNq-*`* z4d~hVI?^(3K~oB8l)_s%9z&@FN<|~(qEs}ctVq=&A^{os%ec^#f6>ppt3Y%q#ZmK`uMTbVmXAR4+~n7 zszDxb$sN)n*pw#4VV#O)F%}I-8R0g)HKi4JZ@l}OZ=WvU+ch+O!N^TZIL)Dwn=#?1Fz84Oap4$;Ms6mA4GyhuC7s4A zYY5ZDjxh{N*u~0AvC2}|lPdS5Dm}pv>8eBr!1y~RnpTRh7mS3NVT{66=nHr|X)Gok zs2jjA3zyrp0#7U#AtO5WJZ3=(~(oKqs2u4~#HEiozTiQ3>&+11$(7Frr2u z?Vv`%w*J8>+CMi%T8N63R`FtJ>vYk*E7yQ0odq%}-GeEl(<77A1Lz!r$%cYqzi27K z!&QgS$x%k$gEER9l(Fg&8R9QjNV6qp`4XL_l$7mt4;*F8dwvEOuDi)4kpwRzDj1Uv zeAYcIX>6bS7G`9|yt{zGT4mntqP5z*doiuG=G}JY?i{oW3fbo##-3Y}l%Wt6V%}|( zm?TvoQ|2#8yVS<`e?NENHnR3nWHP3widI;q_E)j~6s}*FxFul|J4Wf4>Id#$;+DU8 z0Jppcur>%gCAq~fSqaNOPFeG(`)j>ZZ} zUp1=Co#}fPQOz)e-V{Vd_4KhM%8wICu=tkv<2xky8`ATMmKYIV6_1GLa;9jDH6|`0iBC>VOSdmrwAkUw$#WMJ6?;}yR;{hwpw{XQ z=Gd8%?fVfn(gch4M^D1-SE8k`zJ;4W$an)wKklZ7bkcugDU?G+wGAdCL_6#LLo%S{ zPJf;p^!_2(bQ5Cb+gLIOj}Qt!OXh^`p+Y){U@dN1Qp<>K+i^7;Cgrzopjvmr-IoBbJOwFoN2S0*4wY zIC)U{ZB*e>nDS4=K(+V}1vClKJB}>nrKE#?gA#`LYu_ z@tcvxDe`82o^^M#qzdR8 z)~bvdFmFqEfLC(8U&-TGqsA*pxktQ_O^%^0{k{~;&!=~!;zls<+Oif3hQL|&+D#J^ zHjyrm2hVdR8&z0|PJ_T7@udVDUBWVP8y6U51zpQ1u)b*V+t9ecmX-8gVv{~RZVO^V zOo7IyvqC~*@FF^*3|~LU7h{-4Bl@#UpUy{MNxbC>$S%u9kR7~?khf(tPb)l!Sh!{M zqDHVINNyQjq!FHJJHxb$?ota$2&-F0tJOkmTPZdUs{|7Q@s`mSRI)y#1cmyq(5;rf zNyHoGKq$o)SPBAy0P`t**!m7DMwT`TDFG)4n@NiKl$LbXp-$*k!)xcvKxb>zb|Sp@ z5@)eYlrrH$;{35pAh353=esh2sD2)CPN%U!+eslkan{KM;`vzOJSY~JOT5Y=-N=cg(=@A{ZOUXvU4&r~n8gt+%kYl(K__Wt9Uq2urC|QL`E@v6D zEk<&Gmb4wlbx1ohLU^U~%)|g*&s`{*;BCZ#1PdblG446n; z9;OO8d&wUlfZk1vh)^PWFo_9yG&n!BRRjKOPTi4OwJWt{Du|z8d`QOz1|#vKT+AXY zF+d2vUeixK);vdIF`~tD2Wp7*v6pV6P8>*bYbc6 z_gfGA?7*c1Hx8s9+;Px!m>fBGWaFD#e)Qzg(?@q4yL9X)p*MTK{(fKjy;4-e_YH6W delta 615 zcmZ9HOK2295QeK~c4v30yJy-KWuveuLc~PD^dwmyQOt&*Ap{{Yf}j@_6$J?db5T(j z#ET+0G~&UdM~{mqQBhDMA|V$&8V?d!A2;!ms57&JNPhb7s;>H|q8s%__uWcyUcCil zV`qJARP`Nfg!}4u3*apbkI)cGm5+GfW)yD)65Wz|EfZ6v{;fczq6( zD!0n*N(rEtWr`8|N7doOiIiGNDZ9uvj3tpMuLgb_OoEqXhEaP}N~yG@6i`lOM0O>V zopdU8$vcp^I_xG3S1u>5d@%!-3Lszx&iYjtb9-RUb>N!28@dYfQ1%J7`wI3ap7NW^ zj&_}Ijveui+0Z*^A9%O&+3EbX?zUS>Kd$dZI*Ixs;#H)Fs2?LfNBV;L7b4@dmFqnm zM>(D6`U=OJoE~xgl;ayt-?{$7(HGPw^oYO-L9;^N5O_yWQ|MO$7Xv zOPrQ;N$T4Y?@4+h^?QjQH%nTTIt;KQpy5DI1$aD=+ni# Date: Sun, 20 Oct 2024 18:10:14 +0200 Subject: [PATCH 02/13] mb/lenovo/m900_tiny: disable CLKREQ for SSD and Wi-Fi slots MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's been observed that at least on some M700 Tiny boards, CLKREQ signals aren't wired as per the schematic. Disable them and configure their pads as per original Lenovo UEFI. This change fixes Wi-Fi card detection on M700 Tiny. TEST=Boot M700 Tiny with AX200 card in Wi-Fi card slot and boot to Windows 10. Check that Wi-Fi works correctly. Upstream-Status: Backport Change-Id: I5b26937cd4a6937b516304fefad9186b9e1cdc76 Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/coreboot/+/84813 Reviewed-by: Martin L Roth Tested-by: build bot (Jenkins) Signed-off-by: Michał Kopeć --- src/mainboard/lenovo/m900_tiny/devicetree.cb | 4 ---- src/mainboard/lenovo/m900_tiny/gpio.c | 4 ++-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index 51d3b26798d..269d8b001f9 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -162,8 +162,6 @@ chip soc/intel/skylake end device ref pcie_rp17 on # M.2 2280 / 2242 - SSD register "PcieRpEnable[16]" = "1" - register "PcieRpClkReqSupport[16]" = "1" - register "PcieRpClkReqNumber[16]" = "1" register "PcieRpAdvancedErrorReporting[16]" = "1" register "PcieRpLtrEnable[16]" = "1" register "PcieRpClkSrcNumber[16]" = "7" @@ -171,8 +169,6 @@ chip soc/intel/skylake end device ref pcie_rp7 on # M.2 2230 - WLAN register "PcieRpEnable[6]" = "1" - register "PcieRpClkReqSupport[6]" = "1" - register "PcieRpClkReqNumber[6]" = "11" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieRpClkSrcNumber[6]" = "1" diff --git a/src/mainboard/lenovo/m900_tiny/gpio.c b/src/mainboard/lenovo/m900_tiny/gpio.c index aecea414a28..4c4bac4b8ef 100644 --- a/src/mainboard/lenovo/m900_tiny/gpio.c +++ b/src/mainboard/lenovo/m900_tiny/gpio.c @@ -42,7 +42,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI), PAD_NC(GPP_B5, NONE), - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI), PAD_NC(GPP_B7, NONE), PAD_NC(GPP_B8, NONE), PAD_NC(GPP_B9, NONE), @@ -192,7 +192,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H2, NONE), PAD_NC(GPP_H3, NONE), PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_NC(GPP_H5, NONE), PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, PLTRST, OFF, ACPI), PAD_NC(GPP_H7, NONE), PAD_NC(GPP_H8, NONE), From f9380c50ea9cb7e2cb45f8955bbd2b7987c1880e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sun, 30 Mar 2025 10:38:04 +0200 Subject: [PATCH 03/13] mb/lenovo/m900_tiny: Put options in CFR cbtable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Backport Change-Id: I259f88a3ceb9aee54016bb88a7d4de2b58dffa83 Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/coreboot/+/87048 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel Signed-off-by: Michał Kopeć --- src/mainboard/lenovo/m900_tiny/Kconfig | 2 + src/mainboard/lenovo/m900_tiny/Makefile.mk | 1 + src/mainboard/lenovo/m900_tiny/cfr.c | 79 ++++++++++++++++++++++ src/mainboard/lenovo/m900_tiny/ramstage.c | 35 ++++++++-- 4 files changed, 113 insertions(+), 4 deletions(-) create mode 100644 src/mainboard/lenovo/m900_tiny/cfr.c diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig index 8ad36e0014a..a99afa1b8b5 100644 --- a/src/mainboard/lenovo/m900_tiny/Kconfig +++ b/src/mainboard/lenovo/m900_tiny/Kconfig @@ -6,6 +6,8 @@ if BOARD_LENOVO_THINKCENTRE_M900_TINY config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DRIVERS_EFI_VARIABLE_STORE + select DRIVERS_OPTION_CFR select DRIVERS_UART_8250IO select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/m900_tiny/Makefile.mk b/src/mainboard/lenovo/m900_tiny/Makefile.mk index 44db0910ed2..3b5a2a27a5d 100644 --- a/src/mainboard/lenovo/m900_tiny/Makefile.mk +++ b/src/mainboard/lenovo/m900_tiny/Makefile.mk @@ -7,6 +7,7 @@ bootblock-y += gpio_early.c romstage-y += romstage.c +ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c ramstage-y += gpio.c ramstage-y += hda_verb.c ramstage-y += ramstage.c diff --git a/src/mainboard/lenovo/m900_tiny/cfr.c b/src/mainboard/lenovo/m900_tiny/cfr.c new file mode 100644 index 00000000000..0bd2f8f56e5 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/cfr.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +struct sm_object wifi_slot_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "wifi_slot_enable", + .ui_name = "Enable Wi-Fi card slot", + .ui_helptext = "Enable or disable detection of devices in the Wi-Fi card slot", + .default_value = true, +}); + +struct sm_object ssd_slot_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "ssd_slot_enable", + .ui_name = "Enable SSD slot", + .ui_helptext = "Enable or disable detection of devices in the SSD slot", + .default_value = true, +}); + +struct sm_object hdd_slot_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "hdd_slot_enable", + .ui_name = "Enable 2.5 inch disk slot", + .ui_helptext = "Enable or disable detection of devices in the 2.5 inch disk slot", + .default_value = true, +}); + +static struct sm_obj_form devices = { + .ui_name = "Devices", + .obj_list = (const struct sm_object *[]) { + &wifi_slot_enable, + &ssd_slot_enable, + &hdd_slot_enable, + NULL + }, +}; + +struct sm_object ps2_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "ps2_enable", + .ui_name = "PS/2 controller", + .ui_helptext = "Enable or disable the PS/2 controller", + .default_value = true, +}); + +struct sm_object power_on_after_fail = SM_DECLARE_ENUM({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "power_on_after_fail", + .ui_name = "Power state after fail", + .ui_helptext = "State of the platform after external power is restored", + .default_value = CONFIG_MAINBOARD_POWER_FAILURE_STATE, + .values = (const struct sm_enum_value[]) { + { "Off", 0 }, + { "On", 1 }, + { "Previous", 2 }, + SM_ENUM_VALUE_END }, +}); + +static struct sm_obj_form superio = { + .ui_name = "Super I/O", + .obj_list = (const struct sm_object *[]) { + &ps2_enable, + &power_on_after_fail, + NULL + }, +}; + +static struct sm_obj_form *sm_root[] = { + &devices, + &superio, + NULL +}; + +void mb_cfr_setup_menu(struct lb_cfr *cfr_root) +{ + cfr_write_setup_menu(cfr_root, sm_root); +} diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 6e66f3a7cc7..7eadabe2a21 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -2,10 +2,14 @@ #include #include +#include #include #include #include +#include #include +#include +#include static void print_board_id(void) { @@ -32,19 +36,42 @@ static void print_board_id(void) } printk(BIOS_INFO, "Serial header %spopulated\n", !gpio_get(GPP_A22) ? "" : "un"); - printk(BIOS_INFO, "PS/2 header %spopulated\n", !gpio_get(GPP_D14) ? "" : "un"); - printk(BIOS_INFO, "USB header %spopulated\n", !gpio_get(GPP_C19) ? "" : "un"); - printk(BIOS_INFO, "DisplayPort header %spopulated\n", !gpio_get(GPP_B15) ? "" : "un"); - printk(BIOS_INFO, "PCIe / SATA header %spopulated\n", !gpio_get(GPP_B21) ? "" : "un"); } +static void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + struct device *wifi_dev = DEV_PTR(pcie_rp7); + struct device *ssd_dev = DEV_PTR(pcie_rp17); + struct device *ps2_dev = dev_find_slot_pnp(0x2e, NCT6687D_KBC); + + if (get_uint_option("wifi_slot_enable", 1) == 0) { + cfg->usb2_ports[8].enable = 0; + wifi_dev->enabled = 0; + } + + if (get_uint_option("ssd_slot_enable", 1) == 0) { + cfg->SataPortsEnable[4] = 0; + ssd_dev->enabled = 0; + } + + if (get_uint_option("hdd_slot_enable", 1) == 0) { + cfg->SataPortsEnable[0] = 0; + cfg->SataPortsEnable[1] = 0; + } + + if (get_uint_option("ps2_enable", 1) == 0) + ps2_dev->enabled = 0; +} + static void mainboard_enable(struct device *dev) { mainboard_configure_gpios(); + devtree_update(); print_board_id(); } From 8707394ea7b6d8c0ac95e0fade83caacb85a2ea8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Thu, 24 Oct 2024 19:42:45 +0200 Subject: [PATCH 04/13] mb/lenovo/m900_tiny: enable power LED blink in S3 and S4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The power LED may be disabled by GPP_D1. The pin is PWM capable, so configure it in PWM mode with a frequency of 0.5Hz, duty cycle of 50% when entering sleep. The result is that the power LED toggles on/off every second. TEST=Boot to Windows 10, enter S3, and wake. The power LED will blink when system is asleep and glow continuously when awake. Upstream-Status: Backport Change-Id: I121e0ef3e47aec1cacdace3f2af47a3fdacf69cf Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/coreboot/+/84860 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Felix Held Reviewed-by: Paul Menzel Signed-off-by: Michał Kopeć --- src/mainboard/lenovo/m900_tiny/Makefile.mk | 2 ++ src/mainboard/lenovo/m900_tiny/gpio.c | 2 +- src/mainboard/lenovo/m900_tiny/ramstage.c | 8 ++++++++ src/mainboard/lenovo/m900_tiny/smihandler.c | 22 +++++++++++++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/lenovo/m900_tiny/smihandler.c diff --git a/src/mainboard/lenovo/m900_tiny/Makefile.mk b/src/mainboard/lenovo/m900_tiny/Makefile.mk index 3b5a2a27a5d..d016e93f49a 100644 --- a/src/mainboard/lenovo/m900_tiny/Makefile.mk +++ b/src/mainboard/lenovo/m900_tiny/Makefile.mk @@ -12,3 +12,5 @@ ramstage-y += gpio.c ramstage-y += hda_verb.c ramstage-y += ramstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/m900_tiny/gpio.c b/src/mainboard/lenovo/m900_tiny/gpio.c index 4c4bac4b8ef..101f47b6731 100644 --- a/src/mainboard/lenovo/m900_tiny/gpio.c +++ b/src/mainboard/lenovo/m900_tiny/gpio.c @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_D ------- */ PAD_NC(GPP_D0, NONE), - PAD_NC(GPP_D1, NONE), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF4), /* PW_LED# (blink mode)*/ PAD_NC(GPP_D2, NONE), PAD_NC(GPP_D3, NONE), PAD_NC(GPP_D4, NONE), diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 7eadabe2a21..92ef6b8e67e 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -5,8 +5,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -73,6 +75,12 @@ static void mainboard_enable(struct device *dev) mainboard_configure_gpios(); devtree_update(); print_board_id(); + /* Configure GPIO community 1 PWM frequency to 0.5Hz, 0% duty cycle */ + pcr_write32(PID_GPIOCOM1, 0x204, (1 << 14)); + /* Set the software update flag */ + pcr_or32(PID_GPIOCOM1, 0x204, (1 << 30)); + /* Enable PWM */ + pcr_or32(PID_GPIOCOM1, 0x204, (1 << 31)); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/m900_tiny/smihandler.c b/src/mainboard/lenovo/m900_tiny/smihandler.c new file mode 100644 index 00000000000..6ae0b36a257 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/smihandler.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* Enable blinking power LED when entering S3 or S4 */ + switch (slp_typ) { + case ACPI_S3: + case ACPI_S4: + /* Configure GPIO community 1 PWM duty cycle to 50% */ + pcr_rmw32(PID_GPIOCOM1, 0x204, 0xffffff00, 0x7f); + /* Set the software update flag */ + pcr_or32(PID_GPIOCOM1, 0x204, (1 << 30)); + break; + default: + break; + } +} From 3c8bf25e5e32ebdf11f7342be7016efeb81bf998 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sat, 29 Mar 2025 14:25:11 +0100 Subject: [PATCH 05/13] mb/lenovo/m900_tiny: Enable Vboot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Vboot configuration (Kconfig and FMDs for RO only and RW_A layouts). TEST=Build with UEFIPayload and boot to payload. Verify in cbmem logs that verstage has executed and selected Slot A in the case of RW_A layout. Upstream-Status: Backport Change-Id: Ide2a3a4b59be5b27bf7315690520c9392a98d044 Signed-off-by: Michał Kopeć --- src/mainboard/lenovo/m900_tiny/Kconfig | 11 ++++++ src/mainboard/lenovo/m900_tiny/vboot-ro.fmd | 30 ++++++++++++++++ src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd | 36 ++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 src/mainboard/lenovo/m900_tiny/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig index a99afa1b8b5..05976c634bc 100644 --- a/src/mainboard/lenovo/m900_tiny/Kconfig +++ b/src/mainboard/lenovo/m900_tiny/Kconfig @@ -40,4 +40,15 @@ config PRERAM_CBMEM_CONSOLE_SIZE config DIMM_SPD_SIZE default 512 #DDR4 +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_VBNV_FLASH + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + endif diff --git a/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd new file mode 100644 index 00000000000..40855e7c010 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd @@ -0,0 +1,30 @@ +FLASH 16M { + SI_ALL 8M { + SI_DESC 4K + SI_GBE 8K + SI_ME + } + SI_BIOS 8M { + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + } + + WP_RO { + FMAP 2K + RO_FRID 128 + RO_PADDING 1920 + GBB 120K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd new file mode 100644 index 00000000000..df3bfdb417b --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd @@ -0,0 +1,36 @@ +FLASH 16M { + SI_ALL 8M { + SI_DESC 4K + SI_GBE 8K + SI_ME + } + SI_BIOS 8M { + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + } + + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 128 + } + + WP_RO 3M { + FMAP 2K + RO_FRID 128 + RO_PADDING 1920 + GBB 120K + COREBOOT(CBFS) + } + } +} From 999aada643d354b78907d066702aa4464a95675e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Fri, 25 Jul 2025 21:21:34 +0200 Subject: [PATCH 06/13] mb/lenovo/m900_tiny/Kconfig: disable CFR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow user to select it via menuconfig if they want it. Upstream-Status: Pending Change-Id: Iefe8ec161c1266af3568695f06b5bf500f94f4b1 Signed-off-by: Michał Kopeć --- src/mainboard/lenovo/m900_tiny/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig index 05976c634bc..43dea9c0f70 100644 --- a/src/mainboard/lenovo/m900_tiny/Kconfig +++ b/src/mainboard/lenovo/m900_tiny/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select DRIVERS_EFI_VARIABLE_STORE - select DRIVERS_OPTION_CFR select DRIVERS_UART_8250IO select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES From a82fda5ead22cf63262219632101abcb8137bd3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Fri, 25 Jul 2025 21:22:08 +0200 Subject: [PATCH 07/13] mb/lenovo/m900_tiny/Kconfig: select VBOOT_NO_BOARD_SUPPORT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes compilation which failed due to missing function definitions for e.g. recovery switch. Upstream-Status: Pending Change-Id: I11b6da0587b3e7f37ed78bb9d5da2bfce7cca9e9 Signed-off-by: Michał Kopeć --- src/mainboard/lenovo/m900_tiny/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig index 43dea9c0f70..a95188f3eb7 100644 --- a/src/mainboard/lenovo/m900_tiny/Kconfig +++ b/src/mainboard/lenovo/m900_tiny/Kconfig @@ -46,6 +46,7 @@ config VBOOT select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select HAS_RECOVERY_MRC_CACHE select VBOOT_VBNV_FLASH + select VBOOT_NO_BOARD_SUPPORT config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT From febcfec616b3de10a358b08c9c1472c020569c7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sat, 26 Jul 2025 00:12:51 +0200 Subject: [PATCH 08/13] mb/lenovo/m900_tiny/ramstage.c: hook up Dasharo options MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I1cd6916191ddf45cf5f9c5a82c965e476595c11c Signed-off-by: Michał Kopeć --- src/mainboard/lenovo/m900_tiny/ramstage.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 92ef6b8e67e..7498babff4d 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -51,7 +52,7 @@ static void devtree_update(void) struct device *ssd_dev = DEV_PTR(pcie_rp17); struct device *ps2_dev = dev_find_slot_pnp(0x2e, NCT6687D_KBC); - if (get_uint_option("wifi_slot_enable", 1) == 0) { + if (get_uint_option("wifi_slot_enable", get_wireless_option()) == 0) { cfg->usb2_ports[8].enable = 0; wifi_dev->enabled = 0; } @@ -66,7 +67,7 @@ static void devtree_update(void) cfg->SataPortsEnable[1] = 0; } - if (get_uint_option("ps2_enable", 1) == 0) + if (get_uint_option("ps2_enable", get_ps2_option()) == 0) ps2_dev->enabled = 0; } From 00964d3a6aaf2a079b4cab0d21fa541c95497dcb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sat, 26 Jul 2025 00:13:12 +0200 Subject: [PATCH 09/13] configs/config.lenovo_m900_tiny: add Dasharo defconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I530e6e2a46e24e485a39a5cd870f07f47e1216d4 Signed-off-by: Michał Kopeć --- configs/config.lenovo_m900_tiny | 50 +++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 configs/config.lenovo_m900_tiny diff --git a/configs/config.lenovo_m900_tiny b/configs/config.lenovo_m900_tiny new file mode 100644 index 00000000000..95b7739ccb3 --- /dev/null +++ b/configs/config.lenovo_m900_tiny @@ -0,0 +1,50 @@ +CONFIG_LOCALVERSION="v0.1.0-rc1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_LENOVO=y +# CONFIG_POST_DEVICE is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +CONFIG_CONSOLE_POST=y +CONFIG_VBOOT_SLOTS_RW_A=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT=5 +CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_INTEL_ME_DISABLED_HECI=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y From 6f071ce476af4c51e1cc915f5f9d641601f42906 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sat, 26 Jul 2025 10:29:19 +0200 Subject: [PATCH 10/13] cpu/x86/mp_init.c: mp_park_aps: make the AP parking timeout work MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Calling stopwatch_duration_msecs causes the stopwatch to stop, which means the timeout would never occur. Use stopwatch_expired instead. Upstream-Status: Pending Change-Id: I312a8c49cf8ac900b4474d18b43576ad9ead036a Signed-off-by: Michał Kopeć --- src/cpu/x86/mp_init.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3dcda4fa9ba..b19a8a8a45a 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1055,17 +1055,17 @@ enum cb_err mp_park_aps(void) enum cb_err ret; long duration_msecs; - stopwatch_init(&sw); - atomic_set(&parked_ap_count, 0); ret = mp_run_on_aps(park_this_cpu, NULL, MP_RUN_ON_ALL_CPUS, 1000 * USECS_PER_MSEC); + stopwatch_init_msecs_expire(&sw, 500); + while (atomic_read(&parked_ap_count) < global_num_aps) { - if ((duration_msecs = stopwatch_duration_msecs(&sw)) > 500) { - printk(BIOS_DEBUG, "%s failed, %d / %d CPUs parked after %ld msecs\n", - __func__, atomic_read(&parked_ap_count), global_num_aps, duration_msecs); + if (stopwatch_expired(&sw)) { + printk(BIOS_DEBUG, "%s failed, %d / %d CPUs parked after 500 msecs\n", + __func__, atomic_read(&parked_ap_count), global_num_aps); return CB_ERR; } From b542eed1d8ef503f99a3950c39b11fdb059cf45b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Fri, 25 Jul 2025 23:58:48 +0200 Subject: [PATCH 11/13] include/cpu/x86/lapic.h: increment the parked AP count in stop_this_cpu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I4d9212c2bd845063df145544d675fb735286bc3c Signed-off-by: Michał Kopeć --- src/include/cpu/x86/lapic.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index a5812fde046..bd448e3df15 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -175,6 +175,7 @@ static __always_inline void lapic_send_ipi_others(uint32_t icrlow) */ static __always_inline void stop_this_cpu(void) { + atomic_inc(&parked_ap_count); /* Called by an AP when it is ready to halt and wait for a new task */ halt(); } From 70b39fe273deaa326aec7f64ab1e1a5c6df2695a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sat, 26 Jul 2025 10:42:30 +0200 Subject: [PATCH 12/13] mb/lenovo/m900_tiny/vboot-r*: add BOOTSPLASH region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3795b154349ddcafd501ed861f2a40ccafc1a74c Signed-off-by: Michał Kopeć --- src/mainboard/lenovo/m900_tiny/vboot-ro.fmd | 1 + src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd index 40855e7c010..2d40edd4392 100644 --- a/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd +++ b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd @@ -17,6 +17,7 @@ FLASH 16M { VBLOCK_DEV 8K } RW_NVRAM(PRESERVE) 24K + BOOTSPLASH(CBFS) 1M } WP_RO { diff --git a/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd index df3bfdb417b..863f0ec1385 100644 --- a/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd +++ b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd @@ -17,6 +17,7 @@ FLASH 16M { VBLOCK_DEV 8K } RW_NVRAM(PRESERVE) 24K + BOOTSPLASH(CBFS) 1M } RW_SECTION_A 3M { From 0bde90e799ca85007e6c9113e280d08db0610bd9 Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Mon, 19 May 2025 22:00:31 +0200 Subject: [PATCH 13/13] configs/config.lenovo_m920q: new platform Notes: - blobs are extracted from original Lenovo firmware and are not uploaded anywhere (yet?); ME image would need to be reconstructed first based on a clean one - [EMERG] ASSERTION ERROR: file 'src/soc/intel/cannonlake/pmutil.c', line 157 Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I1658ef9c430ab21b2567538442744f49745defa1 Signed-off-by: Maciej Pijanowski --- configs/config.lenovo_m920q | 45 +++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 configs/config.lenovo_m920q diff --git a/configs/config.lenovo_m920q b/configs/config.lenovo_m920q new file mode 100644 index 00000000000..022159bacc1 --- /dev/null +++ b/configs/config.lenovo_m920q @@ -0,0 +1,45 @@ +CONFIG_VENDOR_LENOVO=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_LENOVO_M920Q=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_GBE_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPO_CUSTOM=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="04af20830d1108571f3ed35341ecadbcb310f48d" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y