Merge tag 'xilinx-for-v2025.04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

AMD/Xilinx changes for v2025.04-rc4

Zynq:
- Guard code around SPL_FS_LOAD_PAYLOAD_NAME

Versal*:
- Remove tftp block size 4096

Versal:
- Use clocks per DT binding
- Store driver data in data section

Versal Gen 2:
- Fix major/minor version decoding

Author: trini

arch/arm/mach-versal2/include/mach/hardware.h

@@ -51,7 +51,8 @@ struct crp_regs {
 #define PMC_TAP_VERSION		(PMC_TAP + 0x4)
 # define PMC_VERSION_MASK	GENMASK(7, 0)
 # define PS_VERSION_MASK	GENMASK(15, 8)
-# define PS_VERSION_PRODUCTION	0x20
+# define PS_VERSION_MAJOR	GENMASK(7, 4)
+# define PS_VERSION_MINOR	GENMASK(3, 0)
 # define RTL_VERSION_MASK	GENMASK(23, 16)
 # define PLATFORM_MASK		GENMASK(27, 24)
 # define PLATFORM_VERSION_MASK	GENMASK(31, 28)

board/xilinx/zynq/board.c

@@ -179,6 +179,7 @@ void set_dfu_alt_info(char *interface, char *devstr)
 	memset(buf, 0, sizeof(buf));
 
 	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
 	case ZYNQ_BM_SD:
 		snprintf(buf, DFU_ALT_BUF_LEN,
 			 "mmc 0=boot.bin fat 0 1;"
@@ -192,6 +193,7 @@ void set_dfu_alt_info(char *interface, char *devstr)
 			 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
 			 CONFIG_SYS_SPI_U_BOOT_OFFS);
 		break;
+#endif
 #endif
 	default:
 		return;

configs/amd_versal2_virt_defconfig

@@ -70,7 +70,6 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_LWIP=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_CLK_CCF=y
 CONFIG_CLK_SCMI=y

configs/xilinx_versal_net_virt_defconfig

@@ -70,7 +70,6 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_LWIP=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_CLK_VERSAL=y
 CONFIG_DFU_RAM=y

configs/xilinx_versal_virt_defconfig

@@ -74,7 +74,6 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_LWIP=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_CLK_VERSAL=y
 CONFIG_DFU_TIMEOUT=y

drivers/clk/clk_versal.c

@@ -106,8 +106,8 @@ struct versal_clk_priv {
 	struct versal_clock *clk;
 };
 
-static ulong pl_alt_ref_clk;
-static ulong ref_clk;
+static ulong pl_alt_ref_clk __section(".data");
+static ulong ref_clk __section(".data");
 
 struct versal_pm_query_data {
 	u32 qid;
@@ -116,8 +116,8 @@ struct versal_pm_query_data {
 	u32 arg3;
 };
 
-static struct versal_clock *clock;
-static unsigned int clock_max_idx;
+static struct versal_clock *clock __section(".data");
+static unsigned int clock_max_idx __section(".data");
 
 #define PM_QUERY_DATA	35
 
@@ -679,12 +679,21 @@ static int versal_clk_probe(struct udevice *dev)
 
 	debug("%s\n", __func__);
 
-	ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
+	ret = versal_clock_get_freq_by_name("pl_alt_ref",
 					    dev, &pl_alt_ref_clk);
+	if (ret == -ENODATA) {
+		/* Fallback to old DT binding clk name "pl_alt_ref_clk"	*/
+		ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
+						    dev, &pl_alt_ref_clk);
+	}
 	if (ret < 0)
 		return -EINVAL;
 
-	ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk);
+	ret = versal_clock_get_freq_by_name("ref", dev, &ref_clk);
+	if (ret == -ENODATA) {
+		/* Fallback to old DT binding clk name "ref_clk" */
+		ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk);
+	}
 	if (ret < 0)
 		return -EINVAL;
 

drivers/soc/soc_amd_versal2.c

@@ -35,7 +35,9 @@ static int soc_amd_versal2_get_revision(struct udevice *dev, char *buf, int size
 {
 	struct soc_amd_versal2_priv *priv = dev_get_priv(dev);
 
-	return snprintf(buf, size, "v%d", priv->revision);
+	return snprintf(buf, size, "v%d.%d",
+			(u32)FIELD_GET(PS_VERSION_MAJOR, priv->revision),
+			(u32)FIELD_GET(PS_VERSION_MINOR, priv->revision));
 }
 
 static const struct soc_ops soc_amd_versal2_ops = {