diff --git a/library/SubcircuitLibrary/ina128/INA128-cache.lib b/library/SubcircuitLibrary/ina128/INA128-cache.lib new file mode 100644 index 000000000..fa3be0826 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/INA128-cache.lib @@ -0,0 +1,132 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X strobe 8 50 -350 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ina128/INA128.cir b/library/SubcircuitLibrary/ina128/INA128.cir new file mode 100644 index 000000000..a98ef6939 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/INA128.cir @@ -0,0 +1,33 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\INA128\INA128.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 08:55:40 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_R6-Pad1_ GND ? ? Net-_R3-Pad1_ ? ? lm_741 +X3 ? Net-_R8-Pad1_ GND ? ? Net-_R10-Pad1_ ? ? lm_741 +X2 ? Net-_R3-Pad2_ Net-_R10-Pad2_ ? ? Net-_R4-Pad2_ ? ? lm_741 +R3 Net-_R3-Pad1_ Net-_R3-Pad2_ 40k +R11 Net-_R10-Pad2_ GND 40k +R8 Net-_R8-Pad1_ Net-_R10-Pad1_ 25k +R6 Net-_R6-Pad1_ Net-_R3-Pad1_ 25k +R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 40k +R1 Net-_Q1-Pad1_ Net-_R1-Pad2_ 2.2k +U2 GND Net-_R1-Pad2_ zener +R2 Net-_Q2-Pad2_ Net-_R1-Pad2_ 1k +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ GND eSim_PNP +R5 GND Net-_Q1-Pad2_ 6.8k +R9 Net-_Q3-Pad1_ Net-_R12-Pad2_ 2.2k +U3 GND Net-_R12-Pad2_ zener +R12 Net-_Q4-Pad2_ Net-_R12-Pad2_ 1k +Q4 Net-_Q3-Pad1_ Net-_Q4-Pad2_ Net-_Q3-Pad2_ eSim_PNP +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ GND eSim_PNP +R13 GND Net-_Q3-Pad2_ 6.8k +R4 Net-_R3-Pad2_ Net-_R4-Pad2_ 40k +U1 ? Net-_Q1-Pad1_ Net-_R4-Pad2_ Net-_R6-Pad1_ Net-_Q3-Pad1_ Net-_R8-Pad1_ GND ? PORT +R7 Net-_R4-Pad2_ GND 10k + +.end diff --git a/library/SubcircuitLibrary/ina128/INA128.cir.out b/library/SubcircuitLibrary/ina128/INA128.cir.out new file mode 100644 index 000000000..bc2559722 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/INA128.cir.out @@ -0,0 +1,42 @@ +* d:\fossee\esim\library\subcircuitlibrary\ina128\ina128.cir + +.include lm_741.sub +.include PNP.lib +x1 ? net-_r6-pad1_ gnd ? ? net-_r3-pad1_ ? ? lm_741 +x3 ? net-_r8-pad1_ gnd ? ? net-_r10-pad1_ ? ? lm_741 +x2 ? net-_r3-pad2_ net-_r10-pad2_ ? ? net-_r4-pad2_ ? ? lm_741 +r3 net-_r3-pad1_ net-_r3-pad2_ 40k +r11 net-_r10-pad2_ gnd 40k +r8 net-_r8-pad1_ net-_r10-pad1_ 25k +r6 net-_r6-pad1_ net-_r3-pad1_ 25k +r10 net-_r10-pad1_ net-_r10-pad2_ 40k +r1 net-_q1-pad1_ net-_r1-pad2_ 2.2k +* u2 gnd net-_r1-pad2_ zener +r2 net-_q2-pad2_ net-_r1-pad2_ 1k +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q1-pad2_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ gnd Q2N2907A +r5 gnd net-_q1-pad2_ 6.8k +r9 net-_q3-pad1_ net-_r12-pad2_ 2.2k +* u3 gnd net-_r12-pad2_ zener +r12 net-_q4-pad2_ net-_r12-pad2_ 1k +q4 net-_q3-pad1_ net-_q4-pad2_ net-_q3-pad2_ Q2N2907A +q3 net-_q3-pad1_ net-_q3-pad2_ gnd Q2N2907A +r13 gnd net-_q3-pad2_ 6.8k +r4 net-_r3-pad2_ net-_r4-pad2_ 40k +* u1 ? net-_q1-pad1_ net-_r4-pad2_ net-_r6-pad1_ net-_q3-pad1_ net-_r8-pad1_ gnd ? port +r7 net-_r4-pad2_ gnd 10k +a1 gnd net-_r1-pad2_ u2 +a2 gnd net-_r12-pad2_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ina128/INA128.pro b/library/SubcircuitLibrary/ina128/INA128.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/ina128/INA128.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ina128/INA128.sch b/library/SubcircuitLibrary/ina128/INA128.sch new file mode 100644 index 000000000..cc1065883 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/INA128.sch @@ -0,0 +1,576 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:INA128-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 67829383 +P 6100 2700 +F 0 "X1" H 5900 2700 60 0000 C CNN +F 1 "lm_741" H 6000 2450 60 0000 C CNN +F 2 "" H 6100 2700 60 0000 C CNN +F 3 "" H 6100 2700 60 0000 C CNN + 1 6100 2700 + 1 0 0 1 +$EndComp +$Comp +L lm_741 X3 +U 1 1 678293C3 +P 6200 5850 +F 0 "X3" H 6000 5850 60 0000 C CNN +F 1 "lm_741" H 6100 5600 60 0000 C CNN +F 2 "" H 6200 5850 60 0000 C CNN +F 3 "" H 6200 5850 60 0000 C CNN + 1 6200 5850 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X2 +U 1 1 67829441 +P 9450 3600 +F 0 "X2" H 9250 3600 60 0000 C CNN +F 1 "lm_741" H 9350 3350 60 0000 C CNN +F 2 "" H 9450 3600 60 0000 C CNN +F 3 "" H 9450 3600 60 0000 C CNN + 1 9450 3600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 678294D2 +P 7700 2750 +F 0 "R3" H 7750 2880 50 0000 C CNN +F 1 "40k" H 7750 2700 50 0000 C CNN +F 2 "" H 7750 2730 30 0000 C CNN +F 3 "" V 7750 2800 30 0000 C CNN + 1 7700 2750 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 678295FF +P 9350 5900 +F 0 "R11" H 9400 6030 50 0000 C CNN +F 1 "40k" H 9400 5850 50 0000 C CNN +F 2 "" H 9400 5880 30 0000 C CNN +F 3 "" V 9400 5950 30 0000 C CNN + 1 9350 5900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R8 +U 1 1 6782966B +P 6000 5000 +F 0 "R8" H 6050 5130 50 0000 C CNN +F 1 "25k" H 6050 4950 50 0000 C CNN +F 2 "" H 6050 4980 30 0000 C CNN +F 3 "" V 6050 5050 30 0000 C CNN + 1 6000 5000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 67829CD7 +P 6000 3800 +F 0 "R6" H 6050 3930 50 0000 C CNN +F 1 "25k" H 6050 3750 50 0000 C CNN +F 2 "" H 6050 3780 30 0000 C CNN +F 3 "" V 6050 3850 30 0000 C CNN + 1 6000 3800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 6782A0D3 +P 7750 5900 +F 0 "R10" H 7800 6030 50 0000 C CNN +F 1 "40k" H 7800 5850 50 0000 C CNN +F 2 "" H 7800 5880 30 0000 C CNN +F 3 "" V 7800 5950 30 0000 C CNN + 1 7750 5900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67830C1E +P 2300 1850 +F 0 "R1" H 2350 1980 50 0000 C CNN +F 1 "2.2k" H 2350 1800 50 0000 C CNN +F 2 "" H 2350 1830 30 0000 C CNN +F 3 "" V 2350 1900 30 0000 C CNN + 1 2300 1850 + 0 1 1 0 +$EndComp +$Comp +L zener U2 +U 1 1 67830C97 +P 2350 3300 +F 0 "U2" H 2300 3200 60 0000 C CNN +F 1 "zener" H 2350 3400 60 0000 C CNN +F 2 "" H 2400 3300 60 0000 C CNN +F 3 "" H 2400 3300 60 0000 C CNN + 1 2350 3300 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 67830E0C +P 3000 2500 +F 0 "R2" H 3050 2630 50 0000 C CNN +F 1 "1k" H 3050 2450 50 0000 C CNN +F 2 "" H 3050 2480 30 0000 C CNN +F 3 "" V 3050 2550 30 0000 C CNN + 1 3000 2500 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 67830E65 +P 3500 2550 +F 0 "Q2" H 3400 2600 50 0000 R CNN +F 1 "eSim_PNP" H 3450 2700 50 0000 R CNN +F 2 "" H 3700 2650 29 0000 C CNN +F 3 "" H 3500 2550 60 0000 C CNN + 1 3500 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 67830F00 +P 4150 1750 +F 0 "Q1" H 4050 1800 50 0000 R CNN +F 1 "eSim_PNP" H 4100 1900 50 0000 R CNN +F 2 "" H 4350 1850 29 0000 C CNN +F 3 "" H 4150 1750 60 0000 C CNN + 1 4150 1750 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 67831003 +P 4200 3100 +F 0 "R5" H 4250 3230 50 0000 C CNN +F 1 "6.8k" H 4250 3050 50 0000 C CNN +F 2 "" H 4250 3080 30 0000 C CNN +F 3 "" V 4250 3150 30 0000 C CNN + 1 4200 3100 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 67831265 +P 2350 4100 +F 0 "#PWR01" H 2350 3850 50 0001 C CNN +F 1 "GND" H 2350 3950 50 0000 C CNN +F 2 "" H 2350 4100 50 0001 C CNN +F 3 "" H 2350 4100 50 0001 C CNN + 1 2350 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 2500 5550 2600 +Wire Wire Line + 2350 3000 2350 2050 +Wire Wire Line + 2350 4100 2350 3500 +Wire Wire Line + 2800 2550 2350 2550 +Connection ~ 2350 2550 +Wire Wire Line + 3100 2550 3300 2550 +Wire Wire Line + 4150 1950 4150 2900 +Wire Wire Line + 3600 2750 4150 2750 +Connection ~ 4150 2750 +Wire Wire Line + 2350 1750 2350 1650 +Wire Wire Line + 1850 1650 3950 1650 +Wire Wire Line + 3600 2350 3600 1650 +Connection ~ 3600 1650 +Wire Wire Line + 2350 3700 4650 3700 +Wire Wire Line + 4650 3700 4650 1650 +Wire Wire Line + 4650 1650 4350 1650 +Connection ~ 2350 3700 +Wire Wire Line + 4150 3200 4150 3700 +Connection ~ 4150 3700 +Wire Wire Line + 5550 2500 4650 2500 +Connection ~ 4650 2500 +$Comp +L resistor R9 +U 1 1 678322E4 +P 2400 5300 +F 0 "R9" H 2450 5430 50 0000 C CNN +F 1 "2.2k" H 2450 5250 50 0000 C CNN +F 2 "" H 2450 5280 30 0000 C CNN +F 3 "" V 2450 5350 30 0000 C CNN + 1 2400 5300 + 0 1 1 0 +$EndComp +$Comp +L zener U3 +U 1 1 678322EA +P 2450 6750 +F 0 "U3" H 2400 6650 60 0000 C CNN +F 1 "zener" H 2450 6850 60 0000 C CNN +F 2 "" H 2500 6750 60 0000 C CNN +F 3 "" H 2500 6750 60 0000 C CNN + 1 2450 6750 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 678322F0 +P 3100 5950 +F 0 "R12" H 3150 6080 50 0000 C CNN +F 1 "1k" H 3150 5900 50 0000 C CNN +F 2 "" H 3150 5930 30 0000 C CNN +F 3 "" V 3150 6000 30 0000 C CNN + 1 3100 5950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 678322F6 +P 3600 6000 +F 0 "Q4" H 3500 6050 50 0000 R CNN +F 1 "eSim_PNP" H 3550 6150 50 0000 R CNN +F 2 "" H 3800 6100 29 0000 C CNN +F 3 "" H 3600 6000 60 0000 C CNN + 1 3600 6000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 678322FC +P 4250 5200 +F 0 "Q3" H 4150 5250 50 0000 R CNN +F 1 "eSim_PNP" H 4200 5350 50 0000 R CNN +F 2 "" H 4450 5300 29 0000 C CNN +F 3 "" H 4250 5200 60 0000 C CNN + 1 4250 5200 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 67832302 +P 4300 6550 +F 0 "R13" H 4350 6680 50 0000 C CNN +F 1 "6.8k" H 4350 6500 50 0000 C CNN +F 2 "" H 4350 6530 30 0000 C CNN +F 3 "" V 4350 6600 30 0000 C CNN + 1 4300 6550 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 67832308 +P 2450 7550 +F 0 "#PWR02" H 2450 7300 50 0001 C CNN +F 1 "GND" H 2450 7400 50 0000 C CNN +F 2 "" H 2450 7550 50 0001 C CNN +F 3 "" H 2450 7550 50 0001 C CNN + 1 2450 7550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2450 6450 2450 5500 +Wire Wire Line + 2450 7550 2450 6950 +Wire Wire Line + 2900 6000 2450 6000 +Connection ~ 2450 6000 +Wire Wire Line + 3200 6000 3400 6000 +Wire Wire Line + 4250 5400 4250 6350 +Wire Wire Line + 3700 6200 4250 6200 +Connection ~ 4250 6200 +Wire Wire Line + 2450 5200 2450 5100 +Wire Wire Line + 1500 5100 4050 5100 +Wire Wire Line + 3700 5800 3700 5100 +Connection ~ 3700 5100 +Wire Wire Line + 2450 7150 4750 7150 +Wire Wire Line + 4750 7150 4750 5100 +Wire Wire Line + 4750 5100 4450 5100 +Connection ~ 2450 7150 +Wire Wire Line + 4250 6650 4250 7150 +Connection ~ 4250 7150 +Wire Wire Line + 5650 5950 4750 5950 +Connection ~ 4750 5950 +Wire Wire Line + 6650 2700 7600 2700 +$Comp +L resistor R4 +U 1 1 67833400 +P 9400 2750 +F 0 "R4" H 9450 2880 50 0000 C CNN +F 1 "40k" H 9450 2700 50 0000 C CNN +F 2 "" H 9450 2730 30 0000 C CNN +F 3 "" V 9450 2800 30 0000 C CNN + 1 9400 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7900 2700 9300 2700 +Wire Wire Line + 8900 3450 8450 3450 +Wire Wire Line + 8450 3450 8450 2700 +Connection ~ 8450 2700 +Wire Wire Line + 5550 2850 5550 3750 +Wire Wire Line + 5550 3750 5900 3750 +Wire Wire Line + 6200 3750 7000 3750 +Wire Wire Line + 7000 3750 7000 2700 +Connection ~ 7000 2700 +Wire Wire Line + 5900 4950 5300 4950 +Wire Wire Line + 5300 4950 5300 5700 +Wire Wire Line + 6750 5850 6750 4950 +Wire Wire Line + 6750 4950 6200 4950 +Wire Wire Line + 6750 5850 7650 5850 +Wire Wire Line + 7950 5850 9250 5850 +Wire Wire Line + 8900 3700 8600 3700 +Wire Wire Line + 8600 3700 8600 5850 +Connection ~ 8600 5850 +Wire Wire Line + 5300 5700 5650 5700 +Connection ~ 5300 5050 +Wire Wire Line + 5300 4300 5300 3550 +Wire Wire Line + 5300 3550 5550 3550 +Connection ~ 5550 3550 +$Comp +L PORT U1 +U 3 1 67835794 +P 10950 3600 +F 0 "U1" H 11000 3700 30 0000 C CNN +F 1 "PORT" H 10950 3600 30 0000 C CNN +F 2 "" H 10950 3600 60 0000 C CNN +F 3 "" H 10950 3600 60 0000 C CNN + 3 10950 3600 + -1 0 0 1 +$EndComp +Wire Wire Line + 10000 3600 10700 3600 +Wire Wire Line + 9600 2700 10350 2700 +Wire Wire Line + 10350 2700 10350 3600 +Connection ~ 10350 3600 +$Comp +L PORT U1 +U 7 1 678359B2 +P 10900 5850 +F 0 "U1" H 10950 5950 30 0000 C CNN +F 1 "PORT" H 10900 5850 30 0000 C CNN +F 2 "" H 10900 5850 60 0000 C CNN +F 3 "" H 10900 5850 60 0000 C CNN + 7 10900 5850 + -1 0 0 1 +$EndComp +Wire Wire Line + 9550 5850 10650 5850 +$Comp +L PORT U1 +U 2 1 67836684 +P 1600 1650 +F 0 "U1" H 1650 1750 30 0000 C CNN +F 1 "PORT" H 1600 1650 30 0000 C CNN +F 2 "" H 1600 1650 60 0000 C CNN +F 3 "" H 1600 1650 60 0000 C CNN + 2 1600 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6783673C +P 1850 3700 +F 0 "U1" H 1900 3800 30 0000 C CNN +F 1 "PORT" H 1850 3700 30 0000 C CNN +F 2 "" H 1850 3700 60 0000 C CNN +F 3 "" H 1850 3700 60 0000 C CNN + 4 1850 3700 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 678367F0 +P 1950 5550 +F 0 "U1" H 2000 5650 30 0000 C CNN +F 1 "PORT" H 1950 5550 30 0000 C CNN +F 2 "" H 1950 5550 60 0000 C CNN +F 3 "" H 1950 5550 60 0000 C CNN + 6 1950 5550 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 1950 5300 1950 5050 +Wire Wire Line + 1850 3950 1850 4300 +Connection ~ 2350 1650 +$Comp +L PORT U1 +U 5 1 6783749A +P 1250 5100 +F 0 "U1" H 1300 5200 30 0000 C CNN +F 1 "PORT" H 1250 5100 30 0000 C CNN +F 2 "" H 1250 5100 60 0000 C CNN +F 3 "" H 1250 5100 60 0000 C CNN + 5 1250 5100 + 1 0 0 -1 +$EndComp +Connection ~ 2450 5100 +NoConn ~ 6050 3100 +NoConn ~ 6150 3050 +NoConn ~ 5950 3150 +NoConn ~ 5950 2250 +NoConn ~ 6150 2350 +NoConn ~ 6050 5400 +NoConn ~ 6150 5450 +NoConn ~ 6250 5500 +NoConn ~ 6250 6200 +NoConn ~ 6050 6300 +$Comp +L PORT U1 +U 8 1 67838A6D +P 6200 7100 +F 0 "U1" H 6250 7200 30 0000 C CNN +F 1 "PORT" H 6200 7100 30 0000 C CNN +F 2 "" H 6200 7100 60 0000 C CNN +F 3 "" H 6200 7100 60 0000 C CNN + 8 6200 7100 + 0 -1 -1 0 +$EndComp +NoConn ~ 6200 6850 +$Comp +L PORT U1 +U 1 1 678390B5 +P 6700 1600 +F 0 "U1" H 6750 1700 30 0000 C CNN +F 1 "PORT" H 6700 1600 30 0000 C CNN +F 2 "" H 6700 1600 60 0000 C CNN +F 3 "" H 6700 1600 60 0000 C CNN + 1 6700 1600 + 0 1 1 0 +$EndComp +NoConn ~ 6700 1850 +Wire Wire Line + 1950 5050 5300 5050 +Wire Wire Line + 1850 4300 5300 4300 +$Comp +L resistor R7 +U 1 1 678947F3 +P 10550 4850 +F 0 "R7" H 10600 4980 50 0000 C CNN +F 1 "10k" H 10600 4800 50 0000 C CNN +F 2 "" H 10600 4830 30 0000 C CNN +F 3 "" V 10600 4900 30 0000 C CNN + 1 10550 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 10600 4750 10600 3600 +Connection ~ 10600 3600 +Wire Wire Line + 10600 5050 10600 5850 +Wire Wire Line + 10600 5850 10550 5850 +Connection ~ 10550 5850 +$Comp +L GND #PWR03 +U 1 1 67894C48 +P 10650 6200 +F 0 "#PWR03" H 10650 5950 50 0001 C CNN +F 1 "GND" H 10650 6050 50 0000 C CNN +F 2 "" H 10650 6200 50 0001 C CNN +F 3 "" H 10650 6200 50 0001 C CNN + 1 10650 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10650 6200 10550 6200 +Wire Wire Line + 10550 6200 10550 5850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ina128/INA128.sub b/library/SubcircuitLibrary/ina128/INA128.sub new file mode 100644 index 000000000..1fb11100c --- /dev/null +++ b/library/SubcircuitLibrary/ina128/INA128.sub @@ -0,0 +1,36 @@ +* Subcircuit INA128 +.subckt INA128 ? net-_q1-pad1_ net-_r4-pad2_ net-_r6-pad1_ net-_q3-pad1_ net-_r8-pad1_ gnd ? +* d:\fossee\esim\library\subcircuitlibrary\ina128\ina128.cir +.include lm_741.sub +.include PNP.lib +x1 ? net-_r6-pad1_ gnd ? ? net-_r3-pad1_ ? ? lm_741 +x3 ? net-_r8-pad1_ gnd ? ? net-_r10-pad1_ ? ? lm_741 +x2 ? net-_r3-pad2_ net-_r10-pad2_ ? ? net-_r4-pad2_ ? ? lm_741 +r3 net-_r3-pad1_ net-_r3-pad2_ 40k +r11 net-_r10-pad2_ gnd 40k +r8 net-_r8-pad1_ net-_r10-pad1_ 25k +r6 net-_r6-pad1_ net-_r3-pad1_ 25k +r10 net-_r10-pad1_ net-_r10-pad2_ 40k +r1 net-_q1-pad1_ net-_r1-pad2_ 2.2k +* u2 gnd net-_r1-pad2_ zener +r2 net-_q2-pad2_ net-_r1-pad2_ 1k +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q1-pad2_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ gnd Q2N2907A +r5 gnd net-_q1-pad2_ 6.8k +r9 net-_q3-pad1_ net-_r12-pad2_ 2.2k +* u3 gnd net-_r12-pad2_ zener +r12 net-_q4-pad2_ net-_r12-pad2_ 1k +q4 net-_q3-pad1_ net-_q4-pad2_ net-_q3-pad2_ Q2N2907A +q3 net-_q3-pad1_ net-_q3-pad2_ gnd Q2N2907A +r13 gnd net-_q3-pad2_ 6.8k +r4 net-_r3-pad2_ net-_r4-pad2_ 40k +r7 net-_r4-pad2_ gnd 10k +a1 gnd net-_r1-pad2_ u2 +a2 gnd net-_r12-pad2_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends INA128 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ina128/INA128_Previous_Values.xml b/library/SubcircuitLibrary/ina128/INA128_Previous_Values.xml new file mode 100644 index 000000000..b3a4df619 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/INA128_Previous_Values.xml @@ -0,0 +1 @@ +zenerzenerD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741D:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741D:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/ina128/NPN.lib b/library/SubcircuitLibrary/ina128/NPN.lib new file mode 100644 index 000000000..7f2f03199 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/ina128/PNP.lib b/library/SubcircuitLibrary/ina128/PNP.lib new file mode 100644 index 000000000..0eaa3e257 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/ina128/analysis b/library/SubcircuitLibrary/ina128/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ina128/lm_741-cache.lib b/library/SubcircuitLibrary/ina128/lm_741-cache.lib new file mode 100644 index 000000000..6e9088862 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ina128/lm_741.cir b/library/SubcircuitLibrary/ina128/lm_741.cir new file mode 100644 index 000000000..b79891996 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/ina128/lm_741.cir.out b/library/SubcircuitLibrary/ina128/lm_741.cir.out new file mode 100644 index 000000000..0184209e4 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ina128/lm_741.pro b/library/SubcircuitLibrary/ina128/lm_741.pro new file mode 100644 index 000000000..aa33a9cb7 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/lm_741.pro @@ -0,0 +1,44 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/ina128/lm_741.sch b/library/SubcircuitLibrary/ina128/lm_741.sch new file mode 100644 index 000000000..6a74cf221 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 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U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ina128/lm_741.sub b/library/SubcircuitLibrary/ina128/lm_741.sub new file mode 100644 index 000000000..3842c902f --- /dev/null +++ b/library/SubcircuitLibrary/ina128/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ina128/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/ina128/lm_741_Previous_Values.xml new file mode 100644 index 000000000..b61322bb5 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/ina128/npn_1.lib b/library/SubcircuitLibrary/ina128/npn_1.lib new file mode 100644 index 000000000..4a863e3e9 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/library/SubcircuitLibrary/ina128/pnp_1.lib b/library/SubcircuitLibrary/ina128/pnp_1.lib new file mode 100644 index 000000000..c486429f0 --- /dev/null +++ b/library/SubcircuitLibrary/ina128/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file