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Merge pull request #1532 from IntelPython/fix-test-sycl-device-interface-for-future-dpcpp
Added work-around for breaking change in 2024.1 compiler
2 parents e2d9640 + fbd68b8 commit 71b1640

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libsyclinterface/tests/test_sycl_device_interface.cpp

+7-6
Original file line numberDiff line numberDiff line change
@@ -297,9 +297,7 @@ TEST_P(TestDPCTLSyclDeviceInterface, ChkGetPreferredVectorWidthDouble)
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EXPECT_TRUE(vector_width_double != 0);
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}
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else {
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// FIXME: DPC++ 2023 RT must have a bug, since it returns 1 for
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// devices without aspect::fp64
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// EXPECT_TRUE(vector_width_double == 0);
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EXPECT_TRUE(vector_width_double == 0);
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}
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}
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@@ -311,7 +309,9 @@ TEST_P(TestDPCTLSyclDeviceInterface, ChkGetPreferredVectorWidthHalf)
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if (DPCTLDevice_HasAspect(DRef, DPCTL_SyclAspectToDPCTLAspectType(
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DPCTL_StrToAspectType("fp16"))))
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{
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EXPECT_TRUE(vector_width_half != 0);
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// FIXME: zero value incorrectly returned for CPU in 2024.1,
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// even though aspect::fp16 is true
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EXPECT_TRUE(vector_width_half != 0 || DPCTLDevice_IsCPU(DRef));
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}
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else {
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EXPECT_TRUE(vector_width_half == 0);
@@ -384,13 +384,14 @@ TEST_P(TestDPCTLSyclDeviceInterface, ChkGetNativeVectorWidthHalf)
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if (DPCTLDevice_HasAspect(DRef, DPCTL_SyclAspectToDPCTLAspectType(
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DPCTL_StrToAspectType("fp16"))))
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{
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EXPECT_TRUE(vector_width_half != 0);
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// FIXME: zero value incorrectly returned for CPU in 2024.1,
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// even though aspect::fp16 is true
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EXPECT_TRUE(vector_width_half != 0 || DPCTLDevice_IsCPU(DRef));
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}
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else {
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EXPECT_TRUE(vector_width_half == 0);
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}
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}
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//
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TEST_P(TestDPCTLSyclDeviceInterface, ChkGetMaxReadImageArgs)
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{

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