Step.cpp: fix 32bit/64bit issue

JimKnowler · JimKnowler · commit c4c75ff4740b · 2022-03-27T15:55:40.000+01:00
diff --git a/gtestverilog/lib/Step.cpp b/gtestverilog/lib/Step.cpp
@@ -21,7 +21,7 @@ namespace gtestverilog {
 
         PortValue& value = ports[&portDesc];
 
-        portMask |= (1 << portId);
+        portMask |= (uint64_t(1) << portId);
 
         return value;
     }

Original file line number	Diff line number	Diff line change
`@@ -21,7 +21,7 @@ namespace gtestverilog {`
`21`	`21`
`22`	`22`	`PortValue& value = ports[&portDesc];`
`23`	`23`
`24`		`- portMask \|= (1 << portId);`
	`24`	`+ portMask \|= (uint64_t(1) << portId);`
`25`	`25`
`26`	`26`	`return value;`
`27`	`27`	`}`