GPU/instructions.txt at master · KyleHagy/GPU · GitHub

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    // 0x90e0f0ff sORI s1, s1, 0xFFFFFFFF
    // set all cores high(on) how to set this per SM)
    MEM[0] = 8'h90;
    MEM[1] = 8'he0;
    MEM[2] = 8'hf0;
    MEM[3] = 8'hff;

    // sADDI s2, s2, 0
    MEM[4] = 8'h10;
    MEM[5] = 8'h01;
    MEM[6] = 8'h01;
    MEM[7] = 8'h00;

    // 0x90e0f0ff sORI s1, s1, 0xFFFFFFFF
    // iteration for if a warp has jumped here
    MEM[8] = 8'h90;
    MEM[9] = 8'he0;
    MEM[10] = 8'hf0;
    MEM[11] = 8'hff;

    // 0x30 sMUL s4, s3, s2
    // blockDim.x * blockIdx.x => s3 * s2
    MEM[12] = 8'h30;
    MEM[13] = 8'hb2;
    MEM[14] = 8'h21;
    MEM[15] = 8'h00;

    // 0x31814000 vsADD v2, v1, s4
    // int i = threadIdx.x + blockDim.x * blockIdx.x; Ex: core #4 block #2 = 32*2 + 4 = 68th core
    MEM[16]  = 8'h31;
    MEM[17]  = 8'h81;
    MEM[18] = 8'h40;
    MEM[19] = 8'h00;

    // 0x10028202 sADDI s4, s4, 40
    // Load in 40 into s4 for comparison. Used for vsBLTU s0, v2, s4
    MEM[20] = 8'h10;
    MEM[21] = 8'h02;
    MEM[22] = 8'h82;
    MEM[23] = 8'h02;

    // 0x61604100 vsBLTU v2, s4, 0
    // // If (i < n) If not true set thread#'s bit in s1 reg to 0 (core off).
    MEM[24] = 8'h61;
    MEM[25] = 8'h60;
    MEM[26] = 8'h41;
    MEM[27] = 8'h00;

    // vADDI v3, v2, 960
    // starting at 960, the v2 + 960
    MEM[28] = 8'h93;
    MEM[29] = 8'h01;
    MEM[30] = 8'h01;
    MEM[31] = 8'h3c;

    // vADDI v4, v2, 920
    // starting at 920, the v2 + 920
    MEM[32] = 8'h13;
    MEM[33] = 8'h02;
    MEM[34] = 8'h81;
    MEM[35] = 8'h39;

    // 0x83c20100 vLD v5, 0(v3)  // CHANGE ZERO TO THE SPOT IN MEM Load MEM[v2] into vec reg v3 (load into a)
    MEM[36] = 8'h83;
    MEM[37] = 8'hc2;
    MEM[38] = 8'h01;
    MEM[39] = 8'h00;

    // 0x03430200 vLD v6, 0(v4)  // Load MEM[v2] into vec reg v3 (load into b)
    MEM[40] = 8'h03;
    MEM[41] = 8'h43;
    MEM[42] = 8'h02;
    MEM[43] = 8'h00;

    // 0x63e06200 vBLTU v5, v6, v0
    // if (a[i] < b[i]),  If true set v1 reg to 0 (core off)
    MEM[44] = 8'h63;
    MEM[45] = 8'he0;
    MEM[46] = 8'h62;
    MEM[47] = 8'h00;

    // 0xb3035340 vSUB v7, v6, v5 // c[i] = b[i] - a[i];
    MEM[48] = 8'hb3;
    MEM[49] = 8'h03;
    MEM[50] = 8'h53;
    MEM[51] = 8'h40;

    // 0x90c0f0ff sXORI s1, s1, 0xFFFFFFFF // s0 threads that are off now turn on and vice versa
    MEM[52] = 8'h90;
    MEM[53] = 8'hc0;
    MEM[54] = 8'hf0;
    MEM[55] = 8'hff;

    // 0xb3035300 vADD v7, v6, v5 // c[i] = b[i] + a[i];
    MEM[56] = 8'hb3;
    MEM[57] = 8'h03;
    MEM[58] = 8'h53;
    MEM[59] = 8'h00;

    // 0x90e0f0ff sORI s1, s1, 0xFFFFFFFF
    // set all cores high(on) how to set this per SM)
    MEM[60] = 8'h90;
    MEM[61] = 8'he0;
    MEM[62] = 8'hf0;
    MEM[63] = 8'hff;

    // 0x23807100 vST v7, 0(v3)
    // store all values from v7 into mem
    MEM[64] = 8'h23;
    MEM[65] = 8'h80;
    MEM[66] = 8'h71;
    MEM[67] = 8'h00;

    // 0x73000000 EBREAK //sets the CU to ready
    MEM[68] = 8'h73;
    MEM[69] = 8'h00;
    MEM[70] = 8'h00;
    MEM[71] = 8'h00;

    // set this as next warp (put on CU1) start at 32 threadId
    // sADDI s2, s2, 1
    MEM[72] = 8'h10;
    MEM[73] = 8'h01;
    MEM[74] = 8'h11;
    MEM[75] = 8'h00;

    // Go through previous loop
    // sJAL x31, 8 - where code starts
    MEM[76] = 8'hec;
    MEM[77] = 8'h0f;
    MEM[78] = 8'h80;
    MEM[79] = 8'h00;

    // 0x73000000 EBREAK //sets the CU to ready
    MEM[80] = 8'h73;
    MEM[81] = 8'h00;
    MEM[82] = 8'h00;
    MEM[83] = 8'h00;