Update sys.

Author: sorgelig

sys/hps_io.sv

@@ -891,22 +891,28 @@ always @(posedge clk_sys) begin
 	  11: dout <= vid_pix[31:16];
 	  12: dout <= vid_vtime_hdmi[15:0];
 	  13: dout <= vid_vtime_hdmi[31:16];
+	  14: dout <= vid_ccnt[15:0];
+	  15: dout <= vid_ccnt[31:16];
 	  default dout <= 0;
 	endcase
 end
 
 reg [31:0] vid_hcnt = 0;
 reg [31:0] vid_vcnt = 0;
+reg [31:0] vid_ccnt = 0;
 reg  [7:0] vid_nres = 0;
 reg  [1:0] vid_int  = 0;
 
 always @(posedge clk_vid) begin
 	integer hcnt;
 	integer vcnt;
+	integer ccnt;
 	reg old_vs= 0, old_de = 0, old_vmode = 0;
 	reg [3:0] resto = 0;
 	reg calch = 0;
 
+	if(calch & de) ccnt <= ccnt + 1;
+
 	if(ce_pix) begin
 		old_vs <= vs;
 		old_de <= de;
@@ -927,9 +933,11 @@ always @(posedge clk_vid) begin
 					if(&resto) vid_nres <= vid_nres + 1'd1;
 					vid_hcnt <= hcnt;
 					vid_vcnt <= vcnt;
+					vid_ccnt <= ccnt;
 				end
 				vcnt <= 0;
 				hcnt <= 0;
+				ccnt <= 0;
 				calch <= 1;
 			end
 		end

sys/ltc2308.sv

@@ -102,19 +102,19 @@ end
 
 endmodule
 
-module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000)
+module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000, NUM_CH = 1)
 (
-	input        reset,
-	input        clk,
-
-	inout  [3:0] ADC_BUS,
-	output reg   dout,
-	output       active
+	input         reset,
+	input         clk,
+
+	inout  [3:0]  ADC_BUS,
+	output reg    dout,
+	output        active,
+	output        adc_sync,
+	output [(NUM_CH*12)-1:0] adc_data
 );
 
-wire [11:0] adc_data;
-wire        adc_sync;
-ltc2308 #(1, ADC_RATE, CLK_RATE) adc
+ltc2308 #(NUM_CH, ADC_RATE, CLK_RATE) adc
 (
 	.reset(reset),
 	.clk(clk),
@@ -133,8 +133,8 @@ always @(posedge clk) begin
 		data1 <= data2;
 		data2 <= data3;
 		data3 <= data4;
-		data4 <= adc_data;
-		
+		data4 <= adc_data[11:0];
+
 		sum <= data1+data2+data3+data4;
 
 		if(sum[13:2]<HIST_LOW)  dout <= 0;
@@ -148,7 +148,7 @@ reg [1:0] act;
 always @(posedge clk) begin
 	reg [31:0] onesec;
 	reg old_dout;
-	
+
 	onesec <= onesec + 1;
 	if(onesec>CLK_RATE) begin
 		onesec <= 0;

sys/sys.qip

@@ -16,6 +16,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) v
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) arcade_video.v ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) osd.v ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) yc_out.sv ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2c.v ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2s.v ]

sys/sys_top.v

@@ -475,6 +475,18 @@ always@(posedge clk_sys) begin
 					7: io_dout_sys <= FB_STRIDE;
 				endcase
 			end
+`endif
+`ifndef MISTER_DISABLE_YC
+			if(cmd == 'h41) begin
+				case(cnt[3:0])
+					 0: {pal_en,cvbs,yc_en}    <= io_din[2:0];
+					 1: PhaseInc[15:0]         <= io_din;
+					 2: PhaseInc[31:16]        <= io_din;
+					 3: PhaseInc[39:32]        <= io_din[7:0];
+					 4: ColorBurst_Range[15:0] <= io_din;
+					 5: ColorBurst_Range[16]   <= io_din[0];
+				endcase
+			end
 `endif
 		end
 	end
@@ -1152,6 +1164,9 @@ csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);
 
 reg [23:0] dv_data;
 reg        dv_hs, dv_vs, dv_de;
+wire [23:0] dv_data_osd;
+wire dv_hs_osd, dv_vs_osd, dv_cs_osd;
+
 always @(posedge clk_vid) begin
 	reg [23:0] dv_d1, dv_d2;
 	reg        dv_de1, dv_de2, dv_hs1, dv_hs2, dv_vs1, dv_vs2;
@@ -1161,29 +1176,29 @@ always @(posedge clk_vid) begin
 	reg  [3:0] hss;
 
 	if(ce_pix) begin
-		hss <= (hss << 1) | vga_hs_osd;
+		hss <= (hss << 1) | dv_hs_osd;
 
-		old_hs <= vga_hs_osd;
-		if(~old_hs && vga_hs_osd) begin
-			old_vs <= vga_vs_osd;
+		old_hs <= dv_hs_osd;
+		if(~old_hs && dv_hs_osd) begin
+			old_vs <= dv_vs_osd;
 			if(~&vcnt) vcnt <= vcnt + 1'd1;
-			if(~old_vs & vga_vs_osd) begin
+			if(~old_vs & dv_vs_osd) begin
 				if (vcnt != vcnt_ll || vcnt < vcnt_l) vsz <= vcnt;
 				vcnt_l <= vcnt;
 				vcnt_ll <= vcnt_l;
 			end
-			if(old_vs & ~vga_vs_osd) vcnt <= 0;
+			if(old_vs & ~dv_vs_osd) vcnt <= 0;
 
 			if(vcnt == 1) vde <= 1;
 			if(vcnt == vsz - 3) vde <= 0;
 		end
 
-		dv_de1 <= !{hss,vga_hs_osd} && vde;
-		dv_hs1 <= csync_en ? vga_cs_osd : vga_hs_osd;
-		dv_vs1 <= vga_vs_osd;
+		dv_de1 <= !{hss,dv_hs_osd} && vde;
+		dv_hs1 <= csync_en ? dv_cs_osd : dv_hs_osd;
+		dv_vs1 <= dv_vs_osd;
 	end
 
-	dv_d1  <= vga_data_osd;
+	dv_d1  <= dv_data_osd;
 	dv_d2  <= dv_d1;
 	dv_de2 <= dv_de1;
 	dv_hs2 <= dv_hs1;
@@ -1195,6 +1210,12 @@ always @(posedge clk_vid) begin
 	dv_vs  <= dv_vs2;
 end
 
+`ifndef MISTER_DISABLE_YC
+assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs };
+`else
+assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd };
+`endif
+
 wire hdmi_tx_clk;
 `ifndef MISTER_DEBUG_NOHDMI
 cyclonev_clkselect hdmi_clk_sw
@@ -1330,21 +1351,52 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
 		.csync_o(vgas_cs)
 	);
 
-	wire [23:0] vga_o;
-	wire vga_hs, vga_vs, vga_cs;
+	wire [23:0] vga_o, vga_o_t;
+	wire vga_hs, vga_vs, vga_cs, vga_hs_t, vga_vs_t, vga_cs_t;
 	vga_out vga_out
 	(
 		.clk(clk_vid),
 		.ypbpr_en(ypbpr_en),
 		.hsync(vga_hs_osd),
 		.vsync(vga_vs_osd),
 		.csync(vga_cs_osd),
-		.dout(vga_o),
+		.dout(vga_o_t),
+		.din(vga_data_osd),
+		.hsync_o(vga_hs_t),
+		.vsync_o(vga_vs_t),
+		.csync_o(vga_cs_t)
+	);
+
+`ifndef MISTER_DISABLE_YC
+	reg         pal_en;
+	reg         yc_en;
+	reg         cvbs;
+	reg  [16:0] ColorBurst_Range;
+	reg  [39:0] PhaseInc;
+	wire [23:0] yc_o;
+	wire        yc_hs, yc_vs, yc_cs;
+
+	yc_out yc_out
+	(
+		.clk(clk_vid),
+		.PAL_EN(pal_en),
+		.CVBS(cvbs),
+		.PHASE_INC(PhaseInc),
+		.COLORBURST_RANGE(ColorBurst_Range),
+		.hsync(vga_hs_osd),
+		.vsync(vga_vs_osd),
+		.csync(vga_cs_osd),
+		.dout(yc_o),
 		.din(vga_data_osd),
-		.hsync_o(vga_hs),
-		.vsync_o(vga_vs),
-		.csync_o(vga_cs)
+		.hsync_o(yc_hs),
+		.vsync_o(yc_vs),
+		.csync_o(yc_cs)
 	);
+	
+	assign {vga_o, vga_hs, vga_vs, vga_cs } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } : {yc_o, yc_hs, yc_vs, yc_cs };
+`else
+	assign {vga_o, vga_hs, vga_vs, vga_cs } =  {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } ;
+`endif
 
 	wire cs1 = (vga_fb | vga_scaler) ? vgas_cs : vga_cs;