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sorgeligsorgelig
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Update sys.
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‎Genesis.qpf

+1-30
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Intel and sold by Intel or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
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# Date created = 22:22:04 June 17, 2017
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "16.1"
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DATE = "22:22:04 June 17, 2017"
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# Revisions
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QUARTUS_VERSION = "17.0"
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PROJECT_REVISION = "Genesis"

‎Genesis.qsf

+26-351
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‎Genesis.sv

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//============================================================================
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// FPGAGen port to MiSTer
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// Copyright (c) 2017,2018 Sorgelig
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// Copyright (c) 2017-2019 Sorgelig
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//
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// YM2612 implementation by Jose Tejada Gomez. Twitter: @topapate
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// Original Genesis code: Copyright (c) 2010-2013 Gregory Estrade ([email protected])
@@ -64,7 +64,9 @@ module emu
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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input TAPE_IN,
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//ADC
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inout [3:0] ADC_BUS,
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// SD-SPI
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output SD_SCK,
@@ -117,6 +119,7 @@ module emu
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input OSD_STATUS
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);
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;

‎Genesis_Q13.qpf

-10
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#
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# please keep this file read-only!
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# Quartus changes this file everytime revision is switched,
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# and it will be marked as changed with every commit.
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#
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QUARTUS_VERSION = "13.1"
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DATE = "23:13:02 April 27, 2017"
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# Revisions
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PROJECT_REVISION = "Genesis_Q13"

‎Genesis_Q13.qsf

+16-352
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‎files.qip

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set_global_assignment -name QIP_FILE FX68K/fx68k.qip
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set_global_assignment -name QIP_FILE T80/T80.qip
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set_global_assignment -name QIP_FILE jt12/jt12.qip
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set_global_assignment -name QIP_FILE jt89/jt89.qip
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set_global_assignment -name SYSTEMVERILOG_FILE cheatcodes.sv
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set_global_assignment -name SYSTEMVERILOG_FILE EEPROM_STM95.sv
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set_global_assignment -name VHDL_FILE bram.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
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set_global_assignment -name VERILOG_FILE audio_iir_filter.v
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set_global_assignment -name VERILOG_FILE genesis_lpf.v
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set_global_assignment -name VHDL_FILE vdp_common.vhd
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set_global_assignment -name VHDL_FILE vdp.vhd
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set_global_assignment -name VERILOG_FILE gen_io.v
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set_global_assignment -name SYSTEMVERILOG_FILE teamplayer.sv
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set_global_assignment -name VERILOG_FILE fourway.v
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set_global_assignment -name SYSTEMVERILOG_FILE multitap.sv
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set_global_assignment -name SYSTEMVERILOG_FILE system.sv
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set_global_assignment -name SYSTEMVERILOG_FILE Genesis.sv

‎sys/ltc2308.sv

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//============================================================================
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//
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// LTC2308 controller
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// Copyright (C) 2019 Sorgelig
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//
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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// NUM_CH 1..8
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// Sampling rate = ADC_RATE/NUM_CH
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// ADC_RATE max is ~500KHz
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// CLK_RATE max is ~80MHz
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module ltc2308 #(parameter NUM_CH = 2, ADC_RATE = 96000, CLK_RATE = 50000000)
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(
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input reset,
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input clk,
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inout [3:0] ADC_BUS,
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output reg dout_sync, // toggle with every ADC round
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output reg [(NUM_CH*12)-1:0] dout // 12 bits per channel (unsigned)
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);
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39+
localparam TCONV = CLK_RATE/625000;
40+
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reg sck;
42+
wire sdo = cfg[5];
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assign ADC_BUS[3] = sck;
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wire sdi = ADC_BUS[2];
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assign ADC_BUS[1] = sdo;
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assign ADC_BUS[0] = convst;
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reg convst;
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reg [5:0] cfg;
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reg [31:0] sum;
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wire [31:0] next_sum = sum + ADC_RATE;
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reg [2:0] pin;
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wire [2:0] next_pin = (pin == (NUM_CH-1)) ? 3'd0 : (pin + 1'd1);
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always @(posedge clk) begin
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reg [7:0] tconv;
60+
reg [3:0] bitcnt;
61+
reg [10:0] adcin;
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63+
convst <= 0;
64+
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if(reset) begin
66+
sum <= 0;
67+
tconv <= 0;
68+
bitcnt <= 0;
69+
sck <= 0;
70+
cfg <= 0;
71+
dout <= 0;
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pin <= NUM_CH[2:0]-1'd1;
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end
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else begin
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sum <= next_sum;
76+
if(next_sum >= CLK_RATE) begin
77+
sum <= next_sum - CLK_RATE;
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tconv <= TCONV[7:0];
79+
convst <= 1;
80+
bitcnt <= 12;
81+
cfg <= {1'b1, next_pin[0], next_pin[2:1], 1'b1, 1'b0};
82+
if(!next_pin) dout_sync <= ~dout_sync;
83+
end
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85+
if(tconv) tconv <= tconv - 1'd1;
86+
else if(bitcnt) begin
87+
sck <= ~sck;
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89+
if(sck) cfg <= cfg<<1;
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else begin
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adcin <= {adcin[9:0],sdi};
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bitcnt <= bitcnt - 1'd1;
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if(bitcnt == 1) begin
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dout[pin*12 +:12] <= {adcin,sdi};
95+
pin <= next_pin;
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end
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end
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end
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else sck <= 0;
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end
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end
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endmodule
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module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000)
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(
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input reset,
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input clk,
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inout [3:0] ADC_BUS,
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output reg dout,
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output active
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);
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wire [11:0] adc_data;
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wire adc_sync;
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ltc2308 #(1, ADC_RATE, CLK_RATE) adc
118+
(
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.reset(reset),
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.clk(clk),
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.ADC_BUS(ADC_BUS),
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.dout(adc_data),
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.dout_sync(adc_sync)
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);
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always @(posedge clk) begin
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reg [13:0] data1,data2,data3,data4, sum;
129+
reg adc_sync_d;
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131+
adc_sync_d<=adc_sync;
132+
if(adc_sync_d ^ adc_sync) begin
133+
data1 <= data2;
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data2 <= data3;
135+
data3 <= data4;
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data4 <= adc_data;
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138+
sum <= data1+data2+data3+data4;
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140+
if(sum[13:2]<HIST_LOW) dout <= 0;
141+
if(sum[13:2]>HIST_HIGH) dout <= 1;
142+
end
143+
end
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145+
assign active = |act;
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147+
reg [1:0] act;
148+
always @(posedge clk) begin
149+
reg [31:0] onesec;
150+
reg old_dout;
151+
152+
onesec <= onesec + 1;
153+
if(onesec>CLK_RATE) begin
154+
onesec <= 0;
155+
if(act) act <= act - 1'd1;
156+
end
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158+
old_dout <= dout;
159+
if(old_dout ^ dout) act <= 2;
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end
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endmodule

‎sys/pll_q13.qip

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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll/pll_0002.v ]
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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll/pll_0002.qip ]
4+
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_q13.qip ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.v ]
6+
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_core.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_top.v ]

‎sys/pll_q17.qip

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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.qip ]

‎sys/sys.qip

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set_global_assignment -name QIP_FILE [join [list $::quartus(qip_path) pll_q [regexp -inline {[0-9]+} $quartus(version)] .qip] {}]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
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set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
3-
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
4-
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
5-
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.qip ]
64
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
75
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
@@ -17,10 +15,9 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) a
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
1816
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
1917
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
18+
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
2019
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
2423
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
25-
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
26-
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart

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