Skip to content
This repository was archived by the owner on Sep 4, 2023. It is now read-only.

Commit f6d637b

Browse files
sorgeligsorgelig
committed
Fix some warnings.
1 parent f7eb64b commit f6d637b

File tree

3 files changed

+10
-19
lines changed

3 files changed

+10
-19
lines changed

‎Genesis_Q13.qsf

+2
Original file line numberDiff line numberDiff line change
@@ -375,4 +375,6 @@ set_global_assignment -name VHDL_FILE dpram.vhd
375375
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
376376
set_global_assignment -name VERILOG_FILE Genesis.v
377377
set_global_assignment -name SYSTEMVERILOG_FILE Genesis.sv
378+
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
379+
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
378380
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎Genesis_Q13.srf

+2-13
Original file line numberDiff line numberDiff line change
@@ -17,20 +17,9 @@
1717
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
1818
{ "" "" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "" 0 0 "Quartus II" 0 -1 0 ""}
1919
{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Quartus II" 0 -1 0 ""}
20-
{ "" "" "" "Inferred dual-clock RAM node \"emu:emu\|Virtual_Toplevel:Genesis\|TG68:tg68\|TG68_fast:TG68_fast_inst\|regfile_low_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
21-
{ "" "" "" "Inferred dual-clock RAM node \"emu:emu\|Virtual_Toplevel:Genesis\|TG68:tg68\|TG68_fast:TG68_fast_inst\|regfile_low_rtl_1\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
22-
{ "" "" "" "Inferred dual-clock RAM node \"emu:emu\|Virtual_Toplevel:Genesis\|TG68:tg68\|TG68_fast:TG68_fast_inst\|regfile_high_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
23-
{ "" "" "" "Inferred dual-clock RAM node \"emu:emu\|Virtual_Toplevel:Genesis\|TG68:tg68\|TG68_fast:TG68_fast_inst\|regfile_high_rtl_1\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
24-
{ "" "" "" "Inferred dual-clock RAM node \"emu:emu\|Genesis:Genesis\|TG68:tg68\|TG68_fast:TG68_fast_inst\|regfile_low_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
25-
{ "" "" "" "Inferred dual-clock RAM node \"emu:emu\|Genesis:Genesis\|TG68:tg68\|TG68_fast:TG68_fast_inst\|regfile_low_rtl_1\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
26-
{ "" "" "" "Inferred dual-clock RAM node \"emu:emu\|Genesis:Genesis\|TG68:tg68\|TG68_fast:TG68_fast_inst\|regfile_high_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
27-
{ "" "" "" "Inferred dual-clock RAM node \"emu:emu\|Genesis:Genesis\|TG68:tg68\|TG68_fast:TG68_fast_inst\|regfile_high_rtl_1\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
28-
{ "" "" "" "Inferred RAM node \"emu:emu\|Genesis:Genesis\|TG68KdotC_Kernel:tg68\|regfile_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
29-
{ "" "" "" "Inferred RAM node \"emu:emu\|Genesis:Genesis\|TG68KdotC_Kernel:tg68\|regfile_rtl_1\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
30-
{ "" "" "" "Inferred RAM node \"emu:emu\|Genesis:Genesis\|vdp:vdp\|FIFO_ADDR_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
31-
{ "" "" "" "Inferred RAM node \"emu:emu\|Genesis:Genesis\|TG68KdotC_Kernel:CPU_68K\|regfile_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
32-
{ "" "" "" "Inferred RAM node \"emu:emu\|Genesis:Genesis\|TG68KdotC_Kernel:CPU_68K\|regfile_rtl_1\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
3320
{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
21+
{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
22+
{ "" "" "" "*" { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
3423
{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
3524
{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
3625
{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}

‎sys/ascal.vhd

+6-6
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ ARCHITECTURE rtl OF ascal IS
222222
SIGNAL i_write,i_walt : std_logic;
223223
SIGNAL i_push : std_logic;
224224
SIGNAL i_hburst,i_hbcpt : natural RANGE 0 TO 31;
225-
SIGNAL i_shift : unsigned(N_DW-1 DOWNTO 0);
225+
SIGNAL i_shift : unsigned(N_DW-1 DOWNTO 0) := (others => '0');
226226
SIGNAL i_acpt : natural RANGE 0 TO 7;
227227
TYPE arr_dw IS ARRAY (natural RANGE <>) OF unsigned(N_DW-1 DOWNTO 0);
228228
SIGNAL i_dpram,o_dpram : arr_dw(0 TO BLEN*2-1);
@@ -1137,7 +1137,7 @@ BEGIN
11371137
ELSIF rising_edge(o_clk) THEN
11381138
------------------------------------------------------
11391139
o_mode <=mode; -- <ASYNC> ?
1140-
o_run <=run; -- <ASYNC> ?
1140+
--o_run <=run; -- <ASYNC> ?
11411141

11421142
o_htotal <=htotal; -- <ASYNC> ?
11431143
o_hsstart<=hsstart; -- <ASYNC> ?
@@ -1434,9 +1434,9 @@ BEGIN
14341434
IF rising_edge(o_clk) THEN
14351435
-- Pipeline signals
14361436
o_hpos1<=o_hpos; o_hpos2<=o_hpos1;
1437-
o_alt1 <=o_alt; o_alt2 <=o_alt1; o_alt3 <=o_alt2; o_alt4 <=o_alt3;
1438-
o_copy1<=o_copy; o_copy2<=o_copy1; o_copy3<=o_copy2; o_copy4<=o_copy3;
1439-
o_dcpt1<=o_dcpt; o_dcpt2<=o_dcpt1; o_dcpt3<=o_dcpt2; o_dcpt4<=o_dcpt3;
1437+
o_alt1 <=o_alt; o_alt2 <=o_alt1; o_alt3 <=o_alt2; --o_alt4 <=o_alt3;
1438+
o_copy1<=o_copy; o_copy2<=o_copy1; o_copy3<=o_copy2; --o_copy4<=o_copy3;
1439+
o_dcpt1<=o_dcpt; o_dcpt2<=o_dcpt1; o_dcpt3<=o_dcpt2; --o_dcpt4<=o_dcpt3;
14401440

14411441
o_hpixm1<=o_hpixm;
14421442
o_hpix01<=o_hpix0; o_hpix02<=o_hpix01;
@@ -1529,7 +1529,7 @@ BEGIN
15291529
END PROCESS OLBUF;
15301530

15311531
o_radl<=(o_hcpt-o_hmin+OHRES) MOD OHRES;
1532-
xxx_vposi<=to_integer(o_vpos(23 DOWNTO 12)); -- Simu!
1532+
--xxx_vposi<=to_integer(o_vpos(23 DOWNTO 12)); -- Simu!
15331533

15341534
-----------------------------------------------------------------------------
15351535
-- Output video sweep

0 commit comments

Comments
 (0)