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| 1 | +/************************************************************************* |
| 2 | + * Copyright (c) 2022-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved. |
| 3 | + * |
| 4 | + * See LICENSE for license information. |
| 5 | + ************************************************************************/ |
| 6 | + |
| 7 | +#ifndef TRANSFORMER_ENGINE_COMMON_UTIL_CURANDDX_HPP_ |
| 8 | +#define TRANSFORMER_ENGINE_COMMON_UTIL_CURANDDX_HPP_ |
| 9 | + |
| 10 | +namespace transformer_engine { |
| 11 | +namespace curanddx { |
| 12 | +namespace detail { |
| 13 | + |
| 14 | +inline constexpr unsigned int philox4x32_w32_0 = 0x9E3779B9U; |
| 15 | +inline constexpr unsigned int philox4x32_w32_1 = 0xBB67AE85U; |
| 16 | +inline constexpr unsigned int philox4x32_m4x32_0 = 0xD2511F53U; |
| 17 | +inline constexpr unsigned int philox4x32_m4x32_1 = 0xCD9E8D57U; |
| 18 | + |
| 19 | +__forceinline__ __device__ unsigned int mulhilo32(unsigned int a, unsigned int b, |
| 20 | + unsigned int* hip) { |
| 21 | + *hip = __umulhi(a, b); |
| 22 | + return a * b; |
| 23 | +} |
| 24 | + |
| 25 | +__forceinline__ __device__ uint4 single_round(uint4 ctr, uint2 key) { |
| 26 | + unsigned int hi0; |
| 27 | + unsigned int hi1; |
| 28 | + unsigned int lo0 = mulhilo32(philox4x32_m4x32_0, ctr.x, &hi0); |
| 29 | + unsigned int lo1 = mulhilo32(philox4x32_m4x32_1, ctr.z, &hi1); |
| 30 | + |
| 31 | + uint4 ret = {hi1 ^ ctr.y ^ key.x, lo1, hi0 ^ ctr.w ^ key.y, lo0}; |
| 32 | + return ret; |
| 33 | +} |
| 34 | + |
| 35 | +template <unsigned int Rounds> |
| 36 | +__forceinline__ __device__ uint4 multiple_rounds(uint4 c, uint2 k) { |
| 37 | + for (unsigned int i = 0; i < Rounds - 1; i++) { |
| 38 | + c = single_round(c, k); // 1 |
| 39 | + k.x += philox4x32_w32_0; |
| 40 | + k.y += philox4x32_w32_1; |
| 41 | + } |
| 42 | + return single_round(c, k); // Rounds |
| 43 | +} |
| 44 | + |
| 45 | +template <unsigned int Rounds> |
| 46 | +struct philox4x32_native_state { |
| 47 | + static constexpr unsigned int rounds = Rounds; |
| 48 | + |
| 49 | + uint4 ctr; |
| 50 | + uint2 key; |
| 51 | + |
| 52 | + __forceinline__ __device__ void philox_state_incr() { |
| 53 | + if (++ctr.x) return; |
| 54 | + if (++ctr.y) return; |
| 55 | + if (++ctr.z) return; |
| 56 | + ++ctr.w; |
| 57 | + } |
| 58 | + |
| 59 | + __forceinline__ __device__ void philox_state_incr(size_t n) { |
| 60 | + unsigned int nlo = (unsigned int)(n); |
| 61 | + unsigned int nhi = (unsigned int)(n >> 32); |
| 62 | + |
| 63 | + ctr.x += nlo; |
| 64 | + if (ctr.x < nlo) nhi++; |
| 65 | + |
| 66 | + ctr.y += nhi; |
| 67 | + if (nhi <= ctr.y) return; |
| 68 | + if (++ctr.z) return; |
| 69 | + ++ctr.w; |
| 70 | + } |
| 71 | + |
| 72 | + __forceinline__ __device__ void philox_state_incr_hi(size_t n) { |
| 73 | + unsigned int nlo = (unsigned int)(n); |
| 74 | + unsigned int nhi = (unsigned int)(n >> 32); |
| 75 | + |
| 76 | + ctr.z += nlo; |
| 77 | + if (ctr.z < nlo) nhi++; |
| 78 | + |
| 79 | + ctr.w += nhi; |
| 80 | + } |
| 81 | + |
| 82 | + // offset is the total # of 128bits generated with a single generate4() call |
| 83 | + __forceinline__ __device__ void skip_offset(size_t n) { philox_state_incr(n); } |
| 84 | + |
| 85 | + __forceinline__ __device__ void skip_subsequence(size_t n) { philox_state_incr_hi(n); } |
| 86 | + |
| 87 | + __forceinline__ __device__ void init(size_t seed, size_t subsequence, size_t offset) { |
| 88 | + ctr = make_uint4(0, 0, 0, 0); |
| 89 | + key.x = (unsigned int)seed; |
| 90 | + key.y = (unsigned int)(seed >> 32); |
| 91 | + |
| 92 | + skip_subsequence(subsequence); |
| 93 | + skip_offset(offset); |
| 94 | + } |
| 95 | + |
| 96 | + __forceinline__ __device__ uint4 generate4() { |
| 97 | + auto tmp = multiple_rounds<Rounds>(ctr, key); |
| 98 | + philox_state_incr(); |
| 99 | + return tmp; |
| 100 | + } |
| 101 | +}; |
| 102 | +} // namespace detail |
| 103 | +} // namespace curanddx |
| 104 | +} // namespace transformer_engine |
| 105 | + |
| 106 | +#endif // TRANSFORMER_ENGINE_COMMON_UTIL_CURANDDX_HPP_ |
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