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Copy pathlibrary.asm
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6783 lines (6641 loc) · 212 KB
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; *******************************************************************
; *** This software is copyright 2021 by Michael H Riley ***
; *** You have permission to use, modify, copy, and distribute ***
; *** this software so long as this copyright notice is retained. ***
; *** This software may not be used in commercial applications ***
; *** without express written permission from the author. ***
; *******************************************************************
#ifdef USEEF
readef: ldi 0
bn1 ef1
ori 1
ef1: bn2 ef2
ori 2
ef2: bn3 ef3
ori 4
ef3: bn4 ef4
ori 8
ef4: sep sret
#endif
#ifdef SELFTERM
sep r3
delay: ghi re
shr
plo re
sex r2
delay1: dec re
glo re
bz delay-1
br delay1
f_type: plo re
ghi rf
stxd
glo rf
stxd
ghi rd
stxd
glo rd
stxd
glo re
phi rf
ldi 9
plo rf
ldi delay.1
phi rd
ldi delay.0
plo rd
adi 0
sendlp: bdf sendnb ; jump if no bit
#ifdef INVQ
req
#else
seq
#endif
br sendct
#ifdef INVQ
sendnb: seq
#else
sendnb: req
#endif
br sendct
sendct: sep rd ; perform bit delay
sex r2
sex r2
ghi rf
shrc
phi rf
dec rf
glo rf
bnz sendlp
#ifdef INVQ
seq
#else
req
#endif
sep rd
sep rd
irx
ldxa
plo rd
ldxa
phi rd
ldxa
plo rf
ldx
phi rf
sep sret
f_read: ghi rf
stxd
glo rf
stxd
ghi rd
stxd
glo rd
stxd
ldi 9
plo rf
ldi delay.1
phi rd
ldi delay.0
plo rd
ghi re
phi rf
shr
shr
phi re
#ifdef SEREF1
b1 $
#endif
#ifdef SEREF2
b2 $
#endif
#ifdef SEREF3
b3 $
#endif
#ifdef SEREF4
b4 $
#endif
#ifdef SEREF1I
bn1 $
#endif
#ifdef SEREF2I
bn2 $
#endif
#ifdef SEREF3I
bn3 $
#endif
#ifdef SERPBN4I
bn4 $
#endif
sep rd
ghi rf
phi re
ghi rf
shr
bdf recvlpe
recvlp: ghi rf
shr
#ifdef SEREF1
bn1 recvlp0
#endif
#ifdef SEREF2
bn2 recvlp0
#endif
#ifdef SEREF3
bn3 recvlp0
#endif
#ifdef SEREF4
bn4 recvlp0
#endif
#ifdef SEREF1I
b1 recvlp0
#endif
#ifdef SEREF2I
b2 recvlp0
#endif
#ifdef SEREF3I
b3 recvlp0
#endif
#ifdef SERPBN4I
b4 recvlp0
#endif
ori 128
recvlp1: phi rf
sep rd
dec rf
nop
nop
glo rf
bnz recvlp
#ifdef INVQ
recvdone: seq
#else
recvdone: req
#endif
ghi rf
plo re
irx
ldxa
plo rd
ldxa
phi rd
ldxa
plo rf
ldx
phi rf
glo re
sep sret
recvlp0: br recvlp1
recvlpe: ghi rf
shr
#ifdef SEREF1
bn1 recvlpe0
#endif
#ifdef SEREF2
bn2 recvlpe0
#endif
#ifdef SEREF3
bn3 recvlpe0
#endif
#ifdef SEREF4
bn4 recvlpe0
#endif
#ifdef SEREF1I
b1 recvlpe0
#endif
#ifdef SEREF2I
b2 recvlpe0
#endif
#ifdef SEREF3I
b3 recvlpe0
#endif
#ifdef SERPBN4I
b4 recvlpe0
#endif
ori 128
#ifdef INVQ
seq
#else
req
#endif
recvlpe1: phi rf
sep rd
dec rf
sex r2
sex r2
glo rf
bnz recvlpe
br recvdone
#ifdef INVQ
recvlpe0: req
#else
recvlpe0: seq
#endif
br recvlpe1
#ifdef INVQ
f_setbd: seq
#else
f_setbd: req
#endif
ldi 0
phi rc
plo rc
phi rb
plo rb
#ifdef SEREF1
timalc_o: b1 $
#endif
#ifdef SEREF2
timalc_o: b2 $
#endif
#ifdef SEREF3
timalc_o: b3 $
#endif
#ifdef SEREF4
timalc_o: b4 $
#endif
#ifdef SEREF1I
timalc_o: bn1 $
#endif
#ifdef SEREF2I
timalc_o: bn2 $
#endif
#ifdef SEREF3I
timalc_o: bn3 $
#endif
#ifdef SERPBN4I
timalc_o: bn4 $
#endif
#ifdef SEREF1
end_sb: bn1 $
#endif
#ifdef SEREF2
end_sb: bn2 $
#endif
#ifdef SEREF3
end_sb: bn3 $
#endif
#ifdef SEREF4
end_sb: bn4 $
#endif
#ifdef SEREF1I
end_sb: b1 $
#endif
#ifdef SEREF2I
end_sb: b2 $
#endif
#ifdef SEREF3I
end_sb: b3 $
#endif
#ifdef SERPBN4I
end_sb: b4 $
#endif
#ifdef SEREF1
b1 $
#endif
#ifdef SEREF2
b2 $
#endif
#ifdef SEREF3
b3 $
#endif
#ifdef SEREF4
b4 $
#endif
#ifdef SEREF1I
bn1 $
#endif
#ifdef SEREF2I
bn2 $
#endif
#ifdef SEREF3I
bn3 $
#endif
#ifdef SERPBN4I
bn4 $
#endif
setbd1: inc rc
sex r2
sex r2
#ifdef SEREF1
bn1 setbd1
#endif
#ifdef SEREF2
bn2 setbd1
#endif
#ifdef SEREF3
bn3 setbd1
#endif
#ifdef SEREF4
bn4 setbd1
#endif
#ifdef SEREF1I
b1 setbd1
#endif
#ifdef SEREF2I
b2 setbd1
#endif
#ifdef SEREF3I
b3 setbd1
#endif
#ifdef SERPBN4I
b4 setbd1
#endif
setbd2: inc rb
sex r2
sex r2
#ifdef SEREF1
b1 setbd2
#endif
#ifdef SEREF2
b2 setbd2
#endif
#ifdef SEREF3
b3 setbd2
#endif
#ifdef SEREF4
b4 setbd2
#endif
#ifdef SEREF1I
bn1 setbd2
#endif
#ifdef SEREF2I
bn2 setbd2
#endif
#ifdef SEREF3I
bn3 setbd2
#endif
#ifdef SERPBN4I
bn4 setbd2
#endif
setbd4: glo rb
shr
shr
str r2
glo rc
shr
shr
sm
lbz setbd3
ldi 1
lskp
setbd3: ldi 0
phi rb
glo rc
smi 4
phi re
ghi rb
shr
ghi re
shlc
phi re
timalc_rt: sep sret
f_tty: lbr f_type
f_inmsg: lda r6
lbz return
sep scall
dw f_type
lbr f_inmsg
f_msg: lda rf
lbz return
sep scall
dw f_type
lbr f_msg
f_input: ldi 0
plo ra
inplp: sep scall
dw f_read
plo re
smi 3
lbnz inpgo
inpterm: smi 0
ldi 0
lbr inpdone2
inpdone: ldi 0
shr
inpdone2: str rf
sep sret
inpgo: smi 5
lbz isbs
smi 5
lbz inpdone
glo rc
lbnz inpcnt
ghi rc
lbnz inpcnt
ldi 8
sep scall
dw f_tty
lbr bs2
inpcnt: glo re
str rf
inc rf
smi 08
lbnz nobs
isbs: glo ra
lbz inplp
dec ra
dec rf
inc rc
bs2: ldi 32
sep scall
dw f_tty
ldi 8
sep scall
dw f_tty
lbr inplp
nobs: inc ra
dec rc
lbr inplp
#endif
#ifdef MULDIV16
mdnorm: ghi rc
str r2
ghi rd
xor
shl
ldi 0
shlc
plo re
ghi rc
shl
lbnf mdnorm2
ghi rc
xri 0ffh
phi rc
glo rc
xri 0ffh
plo rc
inc rc
mdnorm2: ghi rd
shl
lbnf mdnorm3
ghi rd
xri 0ffh
phi rd
glo rd
xri 0ffh
plo rd
inc rd
mdnorm3: glo re
sep sret
#endif
#ifdef MUL16
mul16: sex r7
irx
ldxa
plo rd
ldxa
phi rd
ldxa
plo rc
ldx
phi rc
sex r2
sep scall
dw mdnorm
plo re
ldi 0
phi rf
plo rf
mulloop: glo rd
lbnz mulcont
ghi rd
lbnz mulcont
glo re
shr
lbnf mulexit
glo rf
xri 0ffh
plo rf
ghi rf
xri 0ffh
phi rf
inc rf
mulexit: sex r7
ghi rf
stxd
glo rf
stxd
sex r2
sep sret
mulcont: ghi rd
shr
phi rd
glo rd
shrc
plo rd
lbnf mulcont2
glo rc
str r2
glo rf
add
plo rf
ghi rc
str r2
ghi rf
adc
phi rf
mulcont2: glo rc
shl
plo rc
ghi rc
shlc
phi rc
lbr mulloop
#endif
#ifdef DIV16
div16: sex r7
irx
ldxa
plo rd
ldxa
phi rd
ldxa
plo rc
ldx
phi rc
sex r2
sep scall
dw mdnorm
plo re
glo rd
lbnz div16_1
ghi rd
lbnz div16_1
sex r7
ldi 0
stxd
stxd
sex r2
sep sret
div16_1: ldi 0
phi rf
plo rf
phi r8
plo r8
inc r8
d16lp1: ghi rd
ani 128
lbnz divst
glo rd
shl
plo rd
ghi rd
shlc
phi rd
glo r8
shl
plo r8
ghi r8
shlc
phi r8
lbr d16lp1
divst: glo rd
lbnz divgo
ghi rd
lbnz divgo
divret: glo re
shr
lbnf divrt
ghi rf
xri 0ffh
phi rf
glo rf
xri 0ffh
plo rf
inc rf
divrt: sex r7
ghi rf
stxd
glo rf
stxd
sex r2
sep sret
divgo: glo rc
plo r9
ghi rc
phi r9
glo rd
str r2
glo rc
sm
plo rc
ghi rd
str r2
ghi rc
smb
phi rc
lbdf divyes
glo r9
plo rc
ghi r9
phi rc
lbr divno
divyes: glo r8
str r2
glo rf
add
plo rf
ghi r8
str r2
ghi rf
adc
phi rf
divno: ghi rd
shr
phi rd
glo rd
shrc
plo rd
ghi r8
shr
phi r8
glo r8
shrc
plo r8
lbdf divret
lbr divst
#endif
#ifdef MOD16
mod16: sep scall
dw div16
inc r7
inc r7
ghi rc
str r7
dec r7
glo rc
str r7
dec r7
sep sret
#endif
#ifdef ADD16
add16: sex r7
irx
ldxa
irx
add
stxd
ldxa
irx
adc
stxd
dec r7
sex r2
sep sret
#endif
#ifdef SUB16
sub16: sex r7
irx
ldxa
irx
sd
stxd
ldxa
irx
sdb
stxd
dec r7
sex r2
sep sret
#endif
#ifdef AND16
and16: sex r7
irx
ldxa
irx
and
stxd
ldxa
irx
and
stxd
dec r7
sex r2
sep sret
#endif
#ifdef OR16
or16: sex r7
irx
ldxa
irx
or
stxd
ldxa
irx
or
stxd
dec r7
sex r2
sep sret
#endif
#ifdef XOR16
xor16: sex r7
irx
ldxa
irx
xor
stxd
ldxa
irx
xor
stxd
dec r7
sex r2
sep sret
#endif
#ifdef CMP16
true: ldi 0ffh
sex r7
stxd
stxd
sex r2
sep sret
false: ldi 000h
sex r7
stxd
stxd
sex r2
sep sret
#endif
#ifdef EQ16
eq16: sep scall
dw sub16
sex r7
irx
ldxa
or
sex r2
lbz true
lbr false
#endif
#ifdef NE16
ne16: sep scall
dw sub16
sex r7
irx
ldxa
or
sex r2
lbnz true
lbr false
#endif
#ifdef GT16
gt16: sep scall
dw sub16
sex r7
irx
ldxa
or
sex r2
lbz false
ldn r7
shl
lbnf true
lbr false
#endif
#ifdef LT16
lt16: sep scall
dw sub16
sex r7
irx
ldxa
or
sex r2
lbz false
ldn r7
shl
lbdf true
lbr false
#endif
#ifdef GTE16
gte16: sep scall
dw sub16
sex r7
irx
ldxa
or
sex r2
lbz true
ldn r7
shl
lbnf true
lbr false
#endif
#ifdef LTE16
lte16: sep scall
dw sub16
sex r7
irx
ldxa
or
sex r2
lbz true
ldn r7
shl
lbdf true
lbr false
#endif
#ifdef ABS16
abs16: inc r7
inc r7
ldn r7
shl
lbnf absrt
dec r7
ldn r7
xri 0ffh
adi 1
str r7
inc r7
ldn r7
xri 0ffh
adci 0
str r7
absrt: dec r7
dec r7
sep sret
#endif
#ifdef SGN16
sgn16: inc r7
lda r7
str r2
ldn r7
shl
lbdf sgnm
ldn r7
or
lbz sgn0
ldi 0
str r7
dec r7
ldi 1
str r7
dec r7
sep sret
sgnm: ldi 0ffh
str r7
dec r7
str r7
dec r7
sep sret
sgn0: dec r7
dec r7
sep sret
#endif
#ifdef LFSR
lfsr_lp: ldi LFSR_.1
phi r9
ldi LFSR_.0
plo r9
inc r9
inc r9
inc r9
ldn r9
plo re
shr
str r2
glo re
xor
plo re
ldn r2
shr
str r2
glo re
xor
plo re
ldn r2
shr
shr
str r2
glo re
xor
plo re
ldn r2
shr
shr
str r2
glo re
xor
plo re
dec r9
dec r9
dec r9
ldn r9
shl
shlc
str r2
glo re
xor
xri 1
shr
ldn r9
shrc
str r9
inc r9
ldn r9
shrc
str r9
inc r9
ldn r9
shrc
str r9
inc r9
ldn r9
shrc
str r9
dec rc
glo rc
lbnz lfsr_lp
sep sret
#endif
#ifdef RND16
rnd16: ldi 16
plo rc
sep scall ; Shift the register
dw lfsr_lp
ldi LFSR_.1
phi r9
ldi LFSR_.0
plo r9
lda r9