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TEST3.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 14:56:30 January 01, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# TEST3_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
set_global_assignment -name TOP_LEVEL_ENTITY top_level_v1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:56:30 JANUARY 01, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE register_4.v
set_global_assignment -name VERILOG_FILE register_2bit.v
set_global_assignment -name VERILOG_FILE sequence_generator.v
set_global_assignment -name VERILOG_FILE split16_v1.v
set_global_assignment -name VERILOG_FILE nor8_v1.v
set_global_assignment -name VERILOG_FILE join16_v1.v
set_global_assignment -name BDF_FILE instruction_decoder.bdf
set_global_assignment -name BDF_FILE decoder.bdf
set_global_assignment -name VHDL_FILE RAM_TEST_3.vhd
set_global_assignment -name VHDL_FILE RAM_TEST_2.vhd
set_global_assignment -name VHDL_FILE RAM_TEST_1.vhd
set_global_assignment -name BDF_FILE top_level_v1.bdf
set_global_assignment -name VERILOG_FILE FDPE.v
set_global_assignment -name VERILOG_FILE FDC.v
set_global_assignment -name VERILOG_FILE FD.v
set_global_assignment -name VERILOG_FILE FDCE.v
set_global_assignment -name VERILOG_FILE register_16_v1.v
set_global_assignment -name VERILOG_FILE register_8_v1.v
set_global_assignment -name VERILOG_FILE replicate.v
set_global_assignment -name VERILOG_FILE bitwise_inv_v1.v
set_global_assignment -name VERILOG_FILE bitwise_and_v1.v
set_global_assignment -name VERILOG_FILE ALU_v2.v
set_global_assignment -name VERILOG_FILE mux4_1_8_v1.v
set_global_assignment -name VERILOG_FILE mux2_1_8_v1.v
set_global_assignment -name VERILOG_FILE mux2_1_1.v
set_global_assignment -name VERILOG_FILE ripple_adder_v1.v
set_global_assignment -name VERILOG_FILE half_adder.v
set_global_assignment -name VERILOG_FILE full_adder.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform17.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform18.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform19.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform20.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform21.vwf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform22.vwf