mux2_1_8_v1.v

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// functions, and any output files from any of the foregoing 
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// agreement, including, without limitation, that your use is for
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// PROGRAM		"Quartus Prime"
// VERSION		"Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
// CREATED		"Thu Dec 31 23:17:10 2020"

module mux2_1_8_v1(
	SEL,
	A,
	B,
	Z
);


input wire	SEL;
input wire	[7:0] A;
input wire	[7:0] B;
output wire	[7:0] Z;

wire	[7:0] Z_ALTERA_SYNTHESIZED;





mux2_1_1	b2v_inst(
	.A(A[0]),
	.B(B[0]),
	.SEL(SEL),
	.Z(Z_ALTERA_SYNTHESIZED[0]));


mux2_1_1	b2v_inst1(
	.A(A[1]),
	.B(B[1]),
	.SEL(SEL),
	.Z(Z_ALTERA_SYNTHESIZED[1]));


mux2_1_1	b2v_inst2(
	.A(A[2]),
	.B(B[2]),
	.SEL(SEL),
	.Z(Z_ALTERA_SYNTHESIZED[2]));


mux2_1_1	b2v_inst3(
	.A(A[3]),
	.B(B[3]),
	.SEL(SEL),
	.Z(Z_ALTERA_SYNTHESIZED[3]));


mux2_1_1	b2v_inst4(
	.A(A[4]),
	.B(B[4]),
	.SEL(SEL),
	.Z(Z_ALTERA_SYNTHESIZED[4]));


mux2_1_1	b2v_inst5(
	.A(A[5]),
	.B(B[5]),
	.SEL(SEL),
	.Z(Z_ALTERA_SYNTHESIZED[5]));


mux2_1_1	b2v_inst6(
	.A(A[6]),
	.B(B[6]),
	.SEL(SEL),
	.Z(Z_ALTERA_SYNTHESIZED[6]));


mux2_1_1	b2v_inst7(
	.A(A[7]),
	.B(B[7]),
	.SEL(SEL),
	.Z(Z_ALTERA_SYNTHESIZED[7]));

assign	Z = Z_ALTERA_SYNTHESIZED;

endmodule