From 01486bf4914c14389a0bf0d4b42088165e9c0289 Mon Sep 17 00:00:00 2001
From: Kristina Sojakova <sojakova.kristina@gmail.com>
Date: Tue, 2 Jun 2026 15:02:19 +0200
Subject: [PATCH 1/5] Update Core.hs

Removed double halt
---
 src/Core.hs | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/Core.hs b/src/Core.hs
index 5401a98..adbd693 100644
--- a/src/Core.hs
+++ b/src/Core.hs
@@ -396,7 +396,7 @@ execute = do
           let imm' = imm ++# (0 :: BitVector 12)
           pure (ADD, pure base', pure imm')
         Instruction.IType (Env Call) _ _ _ ->
-          lift halt >> empty
+          lift setSyscall >> empty
         Instruction.IType (Env Break) _ _ _ ->
           lift halt >> empty
         Instruction.Nop _ -> empty
@@ -492,12 +492,6 @@ memory = do
       setLines $ \c -> c {ctrlMeRegFwd = Just (rd, res)}
     Instruction.UType _ rd _ ->
       setLines $ \c -> c {ctrlMeRegFwd = Just (rd, res)}
-    Instruction.IType (Env Call) _ _ _ -> do
-      setSyscall
-    Instruction.IType (Env Break) _ _ _ -> do
-      halt
-    Instruction.Nop Halted -> do
-      halt    
     _ -> pure ()
 
 -- | Commit computations to the register file.

From 8850c3cc7c3fbe0801a75cfd5f3cdfe6b19b4211 Mon Sep 17 00:00:00 2001
From: Kristina Sojakova <sojakova.kristina@gmail.com>
Date: Tue, 2 Jun 2026 15:41:54 +0200
Subject: [PATCH 2/5] Update Instruction.hs

---
 src/Instruction.hs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/Instruction.hs b/src/Instruction.hs
index ad833fc..9e06720 100644
--- a/src/Instruction.hs
+++ b/src/Instruction.hs
@@ -450,6 +450,10 @@ isNopLoadHazardFirstCycle :: Instruction -> Bool
 isNopLoadHazardFirstCycle (Nop LoadHazardFirstCycle) = True
 isNopLoadHazardFirstCycle _ = False
 
+isNopHalted :: Instruction -> Bool
+isNopHalted (Nop Halted) = True
+isNopHalted _ = False
+
 break :: Instruction
 break = IType (Env Break) 0 0 0
 

From 0af78445d9535afc89cf76c0e53fbda4255ae3d9 Mon Sep 17 00:00:00 2001
From: Kristina Sojakova <sojakova.kristina@gmail.com>
Date: Tue, 2 Jun 2026 15:42:42 +0200
Subject: [PATCH 3/5] Update Core.hs

---
 src/Core.hs | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/Core.hs b/src/Core.hs
index adbd693..c402ebb 100644
--- a/src/Core.hs
+++ b/src/Core.hs
@@ -281,8 +281,7 @@ fetch = do
 decode :: (Access f) => CPUM f ()
 decode = do
   input <- ask
-  ctrl <- gets stateCtrl
-  status <- gets stateHalt
+  ctrl <- gets stateCtrl  
 
   ir <-
     if (inputIsInstr input)
@@ -294,6 +293,7 @@ decode = do
   let load_hazard_first_cycle = maybe False isNopLoadHazardFirstCycle (ctrlExInstr ctrl)
   let call_current_cycle = maybe False isCall (ctrlExInstr ctrl)
   let break_current_cycle = maybe False isBreak (ctrlExInstr ctrl)
+  let halted = maybe False isNopHalted (ctrlExInstr ctrl)
 
   let ir'
         -- If a branch was taken in this cycle, we stall.
@@ -309,7 +309,7 @@ decode = do
         -- If a break is executed in this cycle, we halt.
         | break_current_cycle = Nop Halted
         -- If the core is not running anymore, we halt.
-        | status /= Running = Nop Halted
+        | halted = Nop Halted
         -- Otherwise we process the decoded instruction.
         | otherwise = ir
 
@@ -395,10 +395,8 @@ execute = do
             PC -> gets $ pack . stateExPc
           let imm' = imm ++# (0 :: BitVector 12)
           pure (ADD, pure base', pure imm')
-        Instruction.IType (Env Call) _ _ _ ->
-          lift setSyscall >> empty
-        Instruction.IType (Env Break) _ _ _ ->
-          lift halt >> empty
+        Instruction.IType (Env Call) _ _ _ -> empty
+        Instruction.IType (Env Break) _ _ _ -> empty
         Instruction.Nop _ -> empty
 
     rs1 :: MaybeT (CPUM f) (f Word)
@@ -492,6 +490,10 @@ memory = do
       setLines $ \c -> c {ctrlMeRegFwd = Just (rd, res)}
     Instruction.UType _ rd _ ->
       setLines $ \c -> c {ctrlMeRegFwd = Just (rd, res)}
+    Instruction.IType (Env Call) _ _ _ ->
+      setSyscall
+    Instruction.IType (Env Break) _ _ _ ->
+      halt
     _ -> pure ()
 
 -- | Commit computations to the register file.

From 83c1a53f0dd469235cea6cd2a876d9539c1d2d0e Mon Sep 17 00:00:00 2001
From: Kristina Sojakova <sojakova.kristina@gmail.com>
Date: Wed, 3 Jun 2026 14:31:08 +0200
Subject: [PATCH 4/5] Update Instruction.hs

---
 src/Instruction.hs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/Instruction.hs b/src/Instruction.hs
index 9e06720..5cddcdf 100644
--- a/src/Instruction.hs
+++ b/src/Instruction.hs
@@ -22,6 +22,7 @@ module Instruction
     isCall,
     isNopBranchFirstCycle,
     isNopLoadHazardFirstCycle,
+    isNopHalted,
     break,
     loadHazard,
     isLoad,

From d31073a0206362a3170f82133f062131a209d651 Mon Sep 17 00:00:00 2001
From: Kristina Sojakova <sojakova.kristina@gmail.com>
Date: Wed, 3 Jun 2026 14:37:04 +0200
Subject: [PATCH 5/5] Update Core.hs

---
 src/Core.hs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/Core.hs b/src/Core.hs
index c402ebb..34d0b6a 100644
--- a/src/Core.hs
+++ b/src/Core.hs
@@ -502,7 +502,6 @@ writeback = do
   input <- asks inputMem
   ir <- gets stateWbInstr
   res <- gets stateWbAluRes
-  status <- gets stateHalt
 
   case ir of
     Instruction.RType _ rd _ _ -> do