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lines changed Original file line number Diff line number Diff line change @@ -29,7 +29,7 @@ bash Symbiflow_v1.3.0.gz.run
2929
3030# To Run example
3131export INSTALL_DIR=" specify the installpath"
32- export PATH=" $INSTALL_DIR /install /bin:$INSTALL_DIR /install /bin/python:$PATH "
32+ export PATH=" $INSTALL_DIR /quicklogic-arch-defs /bin:$INSTALL_DIR /quicklogic-arch-defs /bin/python:$PATH "
3333source " $INSTALL_DIR /conda/etc/profile.d/conda.sh"
3434conda activate
3535
@@ -39,13 +39,13 @@ ql_symbiflow -h
3939
4040## Run Example Design
4141
42- The example designs are provided in separate directories at $INSTALL_DIR/install /tests:
42+ The example designs are provided in separate directories at $INSTALL_DIR/quicklogic-arch-defs /tests:
4343
44441 . ` counter_16bit ` - simple 16-bit up-counter. The design targets the the device ql-eos-s3 and package PD64.
4545
4646To run the examples, run following commands:
4747``` bash
48- cd $INSTALL_DIR /install /tests/counter_16bit
48+ cd $INSTALL_DIR /quicklogic-arch-defs /tests/counter_16bit
4949ql_symbiflow -compile -d ql-eos-s3 -P pd64 -v counter_16bit.v -t top -p chandalar.pcf
5050
5151```
@@ -129,7 +129,7 @@ conda activate
129129#Execute the help command to display the help
130130ql_symbiflow -h
131131
132- cd $INSTALL_DIR/install /tests/counter_16bit
132+ cd $INSTALL_DIR/quicklogic-arch-defs /tests/counter_16bit
133133
134134# Use iverilog to simulate the design
135135iverilog -o my_design counter_16bit.v counter_16bit_tb.v
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