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Merge pull request #3 from QuickLogic-Corp/memory_libmap
memory libmap support
2 parents b411f22 + 955074d commit a5c00a3

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‎ql-qlf-plugin/Makefile‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ SOURCES = synth_quicklogic.cc \
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ql-dsp-simd.cc \
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ql-dsp-macc.cc \
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ql-bram-split.cc \
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ql-bram-merge.cc \
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ql-dsp-io-regs.cc \
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ql-bram-asymmetric.cc
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@@ -57,12 +58,15 @@ VERILOG_MODULES = $(COMMON)/cells_sim.v \
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$(QLF_K6N10F_DIR)/dsp_sim.v \
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$(QLF_K6N10F_DIR)/primitives_sim.v \
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$(QLF_K6N10F_DIR)/brams_sim.v \
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$(QLF_K6N10F_DIR)/bram_types_sim.v \
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$(QLF_K6N10F_DIR)/sram1024x18.v \
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$(QLF_K6N10F_DIR)/TDP18K_FIFO.v \
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$(QLF_K6N10F_DIR)/ufifo_ctl.v \
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$(QLF_K6N10F_DIR)/ffs_map.v \
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$(QLF_K6N10F_DIR)/dsp_map.v \
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$(QLF_K6N10F_DIR)/dsp_final_map.v \
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$(QLF_K6N10F_DIR)/libmap_brams_map.v \
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$(QLF_K6N10F_DIR)/libmap_brams.txt \
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$(PP3_DIR)/abc9_map.v \
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$(PP3_DIR)/abc9_model.v \
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$(PP3_DIR)/abc9_unmap.v \
@@ -88,8 +92,8 @@ $(PMGEN_OUT_DIR):
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DEPS := $(PMGEN_OUT_DIR)/ql-dsp-pm.h \
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$(PMGEN_OUT_DIR)/ql-dsp-macc.h \
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$(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-write.h \
92-
$(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-read.h
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$(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-write.h \
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$(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-read.h
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$(DEPS): $(PMGEN_PY) | $(PMGEN_OUT_DIR)
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@@ -107,6 +111,9 @@ $(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-write.h: ql-bram-asymmetric-wider-writ
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$(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-read.h: ql-bram-asymmetric-wider-read.pmg
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python3 $(PMGEN_PY) -o $@ -p ql_bram_asymmetric_wider_read ql-bram-asymmetric-wider-read.pmg
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$(QLF_K6N10F_DIR)/bram_types_sim.v: $(QLF_K6N10F_DIR)/generate_bram_types_sim.py
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python3 $^ $@
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install_modules: $(VERILOG_MODULES)
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$(foreach f,$^,install -D $(f) $(YOSYS_DATA_DIR)/quicklogic/$(f);)
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‎ql-qlf-plugin/ql-bram-merge.cc‎

Lines changed: 216 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,216 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2023 N. Engelhardt <[email protected]>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// ============================================================================
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struct QlBramMergeWorker {
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const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
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const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
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// can be used to record parameter values that have to match on both sides
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typedef dict<RTLIL::IdString, RTLIL::Const> MergeableGroupKeyType;
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RTLIL::Module *module;
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dict<MergeableGroupKeyType, pool<RTLIL::Cell*>> mergeable_groups;
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QlBramMergeWorker(RTLIL::Module* module) : module(module)
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{
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for (RTLIL::Cell* cell : module->selected_cells())
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{
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if(cell->type != split_cell_type) continue;
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if(!cell->hasParam(ID(OPTION_SPLIT))) continue;
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if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue;
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mergeable_groups[get_key(cell)].insert(cell);
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}
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}
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static MergeableGroupKeyType get_key(RTLIL::Cell* cell)
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{
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MergeableGroupKeyType key;
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// For now, there are no restrictions on which cells can be merged
58+
(void) cell;
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return key;
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}
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const dict<RTLIL::IdString, RTLIL::IdString>& param_map(bool second)
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{
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static const dict<RTLIL::IdString, RTLIL::IdString> bram1_map = {
65+
{ ID(INIT), ID(INIT1) },
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{ ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) },
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{ ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) },
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{ ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) },
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{ ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) }
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};
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static const dict<RTLIL::IdString, RTLIL::IdString> bram2_map = {
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{ ID(INIT), ID(INIT2) },
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{ ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) },
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{ ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) },
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{ ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) },
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{ ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) }
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};
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if(second)
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return bram2_map;
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else
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return bram1_map;
83+
}
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const dict<RTLIL::IdString, RTLIL::IdString>& port_map(bool second)
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{
87+
static const dict<RTLIL::IdString, RTLIL::IdString> bram1_map = {
88+
{ ID(PORT_A_CLK), ID(PORT_A1_CLK) },
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{ ID(PORT_B_CLK), ID(PORT_B1_CLK) },
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{ ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) },
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{ ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) },
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{ ID(PORT_A_ADDR), ID(PORT_A1_ADDR) },
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{ ID(PORT_B_ADDR), ID(PORT_B1_ADDR) },
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{ ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) },
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{ ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) },
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{ ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) },
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{ ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) },
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{ ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) },
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{ ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) },
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{ ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) },
101+
{ ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) }
102+
};
103+
static const dict<RTLIL::IdString, RTLIL::IdString> bram2_map = {
104+
{ ID(PORT_A_CLK), ID(PORT_A2_CLK) },
105+
{ ID(PORT_B_CLK), ID(PORT_B2_CLK) },
106+
{ ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) },
107+
{ ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) },
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{ ID(PORT_A_ADDR), ID(PORT_A2_ADDR) },
109+
{ ID(PORT_B_ADDR), ID(PORT_B2_ADDR) },
110+
{ ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) },
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{ ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) },
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{ ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) },
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{ ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) },
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{ ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) },
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{ ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) },
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{ ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) },
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{ ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) }
118+
};
119+
120+
if(second)
121+
return bram2_map;
122+
else
123+
return bram1_map;
124+
}
125+
126+
void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2)
127+
{
128+
129+
// Create the new cell
130+
RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type);
131+
log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name));
132+
133+
for (auto &it : param_map(false))
134+
{
135+
if(bram1->hasParam(it.first))
136+
merged->setParam(it.second, bram1->getParam(it.first));
137+
}
138+
for (auto &it : param_map(true))
139+
{
140+
if(bram2->hasParam(it.first))
141+
merged->setParam(it.second, bram2->getParam(it.first));
142+
}
143+
144+
for (auto &it : port_map(false))
145+
{
146+
if (bram1->hasPort(it.first))
147+
merged->setPort(it.second, bram1->getPort(it.first));
148+
else
149+
log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name));
150+
}
151+
for (auto &it : port_map(true))
152+
{
153+
if (bram2->hasPort(it.first))
154+
merged->setPort(it.second, bram2->getPort(it.first));
155+
else
156+
log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name));
157+
}
158+
merged->attributes = bram1->attributes;
159+
for (auto attr: bram2->attributes)
160+
if (!merged->has_attribute(attr.first))
161+
merged->attributes.insert(attr);
162+
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// Remove the old cells
164+
module->remove(bram1);
165+
module->remove(bram2);
166+
167+
}
168+
169+
void merge_bram_groups()
170+
{
171+
for (auto &it : mergeable_groups)
172+
{
173+
while (it.second.size() > 1)
174+
{
175+
merge_brams(it.second.pop(), it.second.pop());
176+
}
177+
}
178+
}
179+
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};
181+
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struct QlBramMergePass : public Pass {
183+
184+
QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {}
185+
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void help() override
187+
{
188+
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
189+
log("\n");
190+
log(" ql_bram_merge [selection]\n");
191+
log("\n");
192+
log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n");
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log(" into a TDP36K cell operating in split mode\n");
194+
log("\n");
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}
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198+
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
200+
{
201+
log_header(design, "Executing QL_BRAM_MERGE pass.\n");
202+
203+
size_t argidx = 1;
204+
extra_args(args, argidx, design);
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206+
for (RTLIL::Module* module : design->selected_modules())
207+
{
208+
QlBramMergeWorker worker(module);
209+
worker.merge_bram_groups();
210+
}
211+
}
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} QlBramMergePass;
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PRIVATE_NAMESPACE_END

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