CANFD bringup plan

[Roozki]

To start, look into STM32 HAL for canfd. Potentially, we just use 3rd party libraries.
For receive: stack should support polling, interrupt based, and DMA
For transmit: stack should support blocking (wait until mesage is sent) and DMA.

What done looks like:

1. A draw.io or similar document in the software google drive showing the plan for CANFD stack for STM32s + Teensy 4.1 #19

[douglasichen]

Are you sure DMA is possible for CANFD in STM32/Teensy?

LLMs (with sources) & acanfd-stm32 & acan-t4 suggest that interrupts are neccessary.

https://claude.ai/share/6931e193-6535-4ed1-9eb2-bca0ba127088

[Roozki]

Good catch, its possible, but not needed and doesn't make sense to use.
DMA works via interrupts, but on second thought DMA + CANFD doesn't make a bunch of sense on most MCUs, due to most MCUs having a good hardware-based FIFO specifically for CANFD
The reason to use DMA with CAN or CANFD would be if the FIFO is too small for our application.

For now forget about DMA with CANFD, whats important is that we ensure the CPU doesn't need to handle low-level CAN transactions, but most MCUs are already designed around this idea.

It would totally make sense that the DMA controller just doesn't have the direct connections to CANFD, because why would it need to when CANFD has that functionality baked in.

DMA is a way to configure automatic transfers of data into software-defined queues. A dedicated hardware queue for UART is a lot less common in MCUs, so DMA works very well with UART, but absolutely still uses interrupts. Without interrupts, theres no signal to the CPU to say "hey come get your data while its hot!". DMA without interrupts is like somebody setting a table with food, but never calling anyone to eat.

Why its possible in theory, is that you could have DMA connected to CANFD, but likley would need to go through the CPU. Assuming the DMA controller can access the memory region of the CANFD fifo (which it should, even though it probably can't get triggered by the CAN periph), then the CPU would probably just need to do a small set of operations, just signaling to the DMA to pick up the data in the can queue (probably a single memcpy for any amount of data). On some MCUs the can fifo is very small, so this might make sense but what would make more sense, is just specking out the right hardware for the job. And even in this small edge case, that would basically just amount to an internal DMA transfer (memory->memory).