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WB - Wishbone #23

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Paebbels opened this issue Jul 5, 2020 · 0 comments
Open

WB - Wishbone #23

Paebbels opened this issue Jul 5, 2020 · 0 comments
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Accepting PR Internal Mainly internal interface between components. Memory-Mapped Request: New Interface Add an interface not listed yet. SoC Bus Architecture
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Paebbels commented Jul 5, 2020

Specification

Wishone B.4 Specification

Further resources:

/cc @olofk, @tgingold
@Paebbels Paebbels added Internal Mainly internal interface between components. Request: New Interface Add an interface not listed yet. Accepting PR labels Jul 5, 2020
@Paebbels Paebbels added this to the Backlog milestone Jul 5, 2020
@Paebbels Paebbels mentioned this issue Jul 5, 2020
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