AXI4-Lite Register documentation (part 1)

Author: Paebbels

README.md

@@ -5,8 +5,8 @@
 [![Sourcecode License](https://img.shields.io/badge/code-Apache%202.0-97CA00?longCache=true&style=flat-square&longCache=true&logo=Apache)](LICENSE.md)
 [![Documentation](https://img.shields.io/website?longCache=true&style=flat-square&label=VHDL.github.io%2FPoC&logo=GitHub&logoColor=fff&up_color=blueviolet&up_message=Read%20now%20%E2%9E%9A&url=https%3A%2F%2FVHDL.github.io%2FPoC%2Findex.html)](https://VHDL.github.io/PoC/)
 [![Documentation License](https://img.shields.io/badge/doc-CC--BY%204.0-green?longCache=true&style=flat-square&logo=CreativeCommons&logoColor=fff)](docs/Doc-License.rst)    
-![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat)
-[![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases)
+![Latest tag](https://img.shields.io/github/tag/VHDL/PoC.svg?style=flat)
+[![Latest release](https://img.shields.io/github/release/VHDL/PoC.svg?style=flat)](https://github.com/VHDL/PoC/releases)
 
 <!--
 This library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** - 
@@ -106,7 +106,7 @@ Protocol | Git Clone Command
 HTTPS    | `git clone --recursive https://github.com/VHDL/PoC.git PoC`
 SSH      | `git clone --recursive ssh://[email protected]:VHDL/PoC.git PoC`
 
-[221]: https://github.com/VLSI-EDA/PoC/archive/Vivado.zip
+[221]: https://github.com/VHDL/PoC/archive/master.zip
 [222]: http://VHDL.github.io/PoC/UsingPoC/Download.html
 
 ### 2.3 Configuring PoC on a Local System

docs/Doc-License.rst

@@ -0,0 +1,15 @@
+.. _NS/axi4:
+
+PoC.bus.axi4
+============
+
+These are bus entities....
+
+**Entities**
+
+ * :ref:`IP/axi4lite_xxx`
+
+.. toctree::
+   :hidden:
+
+   todo <axi4_xxx>

docs/IPCores/bus/axi4/index.rst

@@ -0,0 +1,46 @@
+.. _IP/axi4lite_GitVersionRegister:
+
+axi4lite_GitVersionRegister
+###########################
+
+
+Current version of this version Reg is `1`. Use this tcl script for Vivado synth-pre-tcl: [set_BuildVersion.tcl](/uploads/9fdf1898a1797857e11889134c5179d0/set_BuildVersion.tcl)
+
+Generics
+********
+
+| Name | Description |
+|-------|----------|
+| VERSION_FILE_NAME | Path to the Version-mem-file created by `set_BuildVersion.tcl`. Relative to `constant MY_PROJECT_DIR` in `src/PoC/my_project.vhdl` |
+| HEADER_FILE_NAME  | If csv-file with all register spaces is needed, put here the name/path of csv-file. Relative to `constant MY_PROJECT_DIR` in `src/PoC/my_project.vhdl` |
+| INCLUDE_XIL_DNA | Includes Xilinx-DNA-Port. Working for 7-Series and US/US+ Devices. Note: 7-Series has 32 times this "unique" ID. |
+| INCLUDE_XIL_USR_EFUSE | Includes Usr-EFuse. {-Currently not Implemented-} |
+| USER_ID               | 96bit ID, which can be set through PL in synthesis. |
+
+Register Map
+************
+
+All Registers are Read-only. Version Register should always start with offset `0x80000000` (First PL Address).
+
+| Offset | Name | Description |
+|---------|-------|----------|
+| 0x000 | Common.BuildDate                        | 31:24 Day <br> 23:16 Month <br> 15:0 Year |
+| 0x004 | Common.NumberModule_VersionOfVersionReg | 31:8 Reserved <br> 7:0 Version-of-Version-Reg (`1`) |
+| 0x008 | Common.VivadoVersion                    | 31:16 Major <br> 15:8 Minor <br> 7:0 Patch |
+| 0x00C | Common.ProjektName                      | `String` Project-Name (20Byte) |
+| 0x020 | Top.Version                             | 31:24 Major <br> 23:16 Minor <br> 15:8 Patch <br> 7:2 Commits-to-Tag(dev-build) <br> 1 Dirty_untracked <br> 0 Dirty_modified |
+| 0x024 | Top.GitHash                             | Git-Hash 20Bytes. Endianess is reversed in the registers. The order of the registers is reversed as well. |
+| 0x038 | Top.GitDate                             | Commit-Date: 31:24 Day <br> 23:16 Month <br> 15:0 Year |
+| 0x03C | Top.GitTime                             | Commit-Time: 31:24 Hour <br> 23:16 Min <br> 15:8 Sec <br> 7:0 Time-Zone as signed|
+| 0x040 | Top.BranchName_Tag                   | Branch-Name 64Byte |
+| 0x080 | Top.GitURL                           | Git-URL starting after `gitlab.plc2.de/` (128Byte) |
+| 0x100 | UID.UID                              | Only present if `INCLUDE_XIL_DNA` is enabled (16Byte) <br> For US/US+ lower 96bit valid, for Series-7 64bit valid |
+| 0x110 | UID.User_eFuse                          | Only present if `INCLUDE_XIL_USR_EFUSE` is enabled |
+| 0x114 | UID.User_ID                          | 96-bit User_ID set by PL |
+
+Files
+*****
+
+Current implementations gives these *.csv and converted *.h files:
+* [Version_Register.csv](/uploads/2f25caea1127e08aa8a2306504199476/Version_Register.csv)
+* [Version_Register.h](/uploads/58cae3f86d3ab4da98094b09a6d9ae39/Version_Register.h)