Skip to content

Commit db6d0c7

Browse files
gmartinagmartina
committed
removed authors
1 parent fd1cc73 commit db6d0c7

17 files changed

+47
-80
lines changed

‎tb/arith/addw/RunAllTests.pro‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# =============================================================================
2-
# Authors: G. Martin
2+
# Authors:
33
#
44
# License:
55
# =============================================================================

‎tb/arith/addw/arith_addw_Simple.vhdl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
-- vim: tabstop=2:shiftwidth=2:noexpandtab
33
-- kate: tab-width 2; replace-tabs off; indent-width 2;
44
-- =============================================================================
5-
-- Authors: G. Martin
5+
-- Authors:
66
--
77
-- Entity: arith_addw_Simple
88
--

‎tb/arith/addw/arith_addw_TestController.vhdl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
-- vim: tabstop=2:shiftwidth=2:noexpandtab
33
-- kate: tab-width 2; replace-tabs off; indent-width 2;
44
-- =============================================================================
5-
-- Authors: G. Martin
5+
-- Authors:
66
--
77
-- Entity: arith_addw_TestController
88
--

‎tb/arith/addw/arith_addw_TestController_pkg.vhdl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
-- vim: tabstop=2:shiftwidth=2:noexpandtab
33
-- kate: tab-width 2; replace-tabs off; indent-width 2;
44
-- =============================================================================
5-
-- Authors: G. Martin
5+
-- Authors:
66
--
77
-- Entity: arith_addw_TestController_pkg
88
--

‎tb/arith/addw/arith_addw_TestHarness.vhdl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
-- vim: tabstop=2:shiftwidth=2:noexpandtab
33
-- kate: tab-width 2; replace-tabs off; indent-width 2;
44
-- =============================================================================
5-
-- Authors: G. Martin
5+
-- Authors:
66
--
77
-- Entity: arith_addw_TestHarness
88
--

‎tb/arith/counter_bcd/RunAllTests.pro‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# =============================================================================
2-
# Authors: G. Martin
2+
# Authors:
33
#
44
# License:
55
# =============================================================================

‎tb/arith/counter_bcd/arith_counter_bcd_Simple.vhdl‎

Lines changed: 31 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
-- vim: tabstop=2:shiftwidth=2:noexpandtab
33
-- kate: tab-width 2; replace-tabs off; indent-width 2;
44
-- =============================================================================
5-
-- Authors: G. Martin
5+
-- Authors:
66
--
77
-- Entity: arith_counter_bcd_Simple
88
--
@@ -38,10 +38,6 @@ library PoC;
3838
use PoC.utils.all;
3939
use PoC.strings.all;
4040
use PoC.physical.all;
41-
-- simulation only packages
42-
--use PoC.sim_types.all;
43-
--use PoC.simulation.all;
44-
--use PoC.waveform.all;
4541

4642
architecture Simple of arith_counter_bcd_TestController is
4743
constant TCID : AlertLogIDType := NewID("CntBCDTest");
@@ -50,52 +46,6 @@ architecture Simple of arith_counter_bcd_TestController is
5046
signal Expected : T_BCD_VECTOR(DIGITS - 1 downto 0);
5147
begin
5248

53-
-- Stimulus generation
54-
StimulusProc: process
55-
begin
56-
Reset_aux <= '0';
57-
wait until Reset = '0';
58-
Reset_aux <= '0';
59-
inc <= '0';
60-
61-
wait until falling_edge(Clock);
62-
Reset_aux <= '1';
63-
inc <= '0';
64-
65-
wait until falling_edge(Clock);
66-
Reset_aux <= '1';
67-
inc <= '1';
68-
69-
wait until falling_edge(Clock);
70-
Reset_aux <= '0';
71-
inc <= '0';
72-
73-
for i in 0 to 10**DIGITS - 1 loop
74-
wait until falling_edge(Clock);
75-
inc <= '1';
76-
77-
wait until falling_edge(Clock);
78-
inc <= '0';
79-
end loop;
80-
81-
wait until falling_edge(Clock);
82-
inc <= '1';
83-
84-
-- Wait 4 more falling edges
85-
for j in 1 to 4 loop
86-
wait until falling_edge(Clock);
87-
end loop;
88-
Reset_aux <= '1';
89-
inc <= '0';
90-
91-
wait until falling_edge(Clock);
92-
Reset_aux <= '0';
93-
inc <= '0';
94-
95-
-- Finalize
96-
WaitForBarrier(TestDone);
97-
end process;
98-
9949
ControlProc: process
10050
constant ProcID : AlertLogIDType := NewID("ControlProc", TCID);
10151
constant TIMEOUT : time := 10 ms;
@@ -125,30 +75,55 @@ begin
12575
constant ProcID : AlertLogIDType := NewID("CheckerProc", TCID);
12676
variable Expected : T_BCD_VECTOR(DIGITS - 1 downto 0);
12777
begin
128-
WaitForClock(Clock);
78+
Reset_aux <= '0';
79+
inc <= '0';
80+
wait until Reset = '0';
81+
12982
WaitForClock(Clock);
13083
Expected := to_BCD_Vector(0, DIGITS);
13184
AffirmIf(ProcID, (Value = Expected), "Wrong initial state. Value=" & to_string(Value));
13285

86+
Reset_aux <= '1';
87+
inc <= '0';
88+
WaitForClock(Clock);
89+
AffirmIf(ProcID, (Value = Expected), "Wrong initial state. Value=" & to_string(Value));
90+
91+
Reset_aux <= '1';
92+
inc <= '1';
13393
WaitForClock(Clock);
13494
AffirmIf(ProcID, (Value = Expected), "Wrong initial state. Value=" & to_string(Value));
95+
Reset_aux <= '0';
96+
inc <= '0';
13597

13698
WaitForClock(Clock);
13799
for i in 1 to 10**DIGITS - 1 loop
138100
Expected := to_BCD_Vector(i, DIGITS);
101+
wait until falling_edge(Clock);
102+
inc <= '1';
103+
WaitForClock(Clock);
104+
wait until falling_edge(Clock);
105+
inc <= '0';
139106
WaitForClock(Clock);
140-
AffirmIf(ProcID, (Value = Expected), "Must be incremented to state " & to_string(Expected) & " Value=" & to_string(Value));
107+
AffirmIf(ProcID, (Value = Expected), "Should be incremented to state " & to_string(Expected) & " Value=" & to_string(Value));
108+
wait until falling_edge(Clock);
109+
inc <= '0';
141110
WaitForClock(Clock);
142-
AffirmIf(ProcID, (Value = Expected), "Must keep the state " & to_string(Expected) & " Value=" & to_string(Value));
111+
AffirmIf(ProcID, (Value = Expected), "Should keep the state " & to_string(Expected) & " Value=" & to_string(Value));
143112
end loop;
144-
113+
wait until falling_edge(Clock);
114+
inc <= '1';
115+
WaitForClock(Clock);
145116
WaitForClock(Clock);
146-
AffirmIf(ProcID, Value = (DIGITS - 1 downto 0 => x"0"), "Should be wrapped to 0000.");
117+
AffirmIf(ProcID, Value = (DIGITS - 1 downto 0 => x"0"), "Should be wrapped to 0000." & " Value=" & to_string(Value));
147118

119+
inc <= '1';
148120
for j in 1 to 5 loop
149121
WaitForClock(Clock);
150122
end loop;
151123

124+
Reset_aux <= '1';
125+
inc <= '0';
126+
WaitForClock(Clock);
152127
WaitForClock(Clock);
153128
AffirmIf(ProcID, Value = (DIGITS - 1 downto 0 => x"0"), "Should be resetted again.");
154129

‎tb/arith/counter_bcd/arith_counter_bcd_TestController.vhdl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
-- vim: tabstop=2:shiftwidth=2:noexpandtab
33
-- kate: tab-width 2; replace-tabs off; indent-width 2;
44
-- =============================================================================
5-
-- Authors: G. Martin
5+
-- Authors:
66
--
77
-- Entity: arith_counter_bcd_TestController
88
--

‎tb/arith/counter_bcd/arith_counter_bcd_TestHarness.vhdl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
-- vim: tabstop=2:shiftwidth=2:noexpandtab
33
-- kate: tab-width 2; replace-tabs off; indent-width 2;
44
-- =============================================================================
5-
-- Authors: G. Martin
5+
-- Authors:
66
--
77
-- Entity: arith_counter_bcd_TestHarness
88
--

‎tb/arith/prefix_and/arith_prefix_and_Exhaustive.vhdl‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,7 @@
22
-- vim: tabstop=2:shiftwidth=2:noexpandtab
33
-- kate: tab-width 2; replace-tabs off; indent-width 2;
44
-- =============================================================================
5-
-- Authors: Thomas B. Preusser
6-
-- Patrick Lehmann
5+
-- Authors:
76
--
87
-- Entity: arith_prefix_and_TestController
98
--

0 commit comments

Comments
 (0)