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Fixed problems reported by PyCharm and Codacy.
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+10
-15
lines changed

2 files changed

+10
-15
lines changed

pyVHDLModel/VHDLModel.py

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,8 @@ class Direction(Enum):
101101
DownTo = 1
102102

103103
def __str__(self):
104-
return ("to", "downto")[self.value] # TODO: check performance
104+
index: int = self.value
105+
return ("to", "downto")[index] # TODO: check performance
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107108
@export
@@ -121,7 +122,8 @@ class Mode(Enum):
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Linkage = 5
122123

123124
def __str__(self):
124-
return ("", "in", "out", "inout", "buffer", "linkage")[self.value] # TODO: check performance
125+
index: int = self.value
126+
return ("", "in", "out", "inout", "buffer", "linkage")[index] # TODO: check performance
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127129
@export
@@ -445,10 +447,10 @@ def __init__(self, subTypeName: Name):
445447
class ConstrainedScalarSubTypeSymbol(SubTypeSymbol):
446448
_range: 'Range'
447449

448-
def __init__(self, subTypeName: Name, r: 'Range' = None):
450+
def __init__(self, subTypeName: Name, rng: 'Range' = None):
449451
super().__init__(subTypeName)
450452
self._subType = None
451-
self._range = r
453+
self._range = rng
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453455
@property
454456
def Range(self) -> 'Range':
@@ -734,6 +736,7 @@ def __init__(self, name: str):
734736
@export
735737
class BaseType(ModelEntity, NamedEntity):
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"""``BaseType`` is the base class of all type entities in this model."""
739+
737740
def __init__(self, name: str):
738741
"""
739742
Initializes underlying ``BaseType``.
@@ -1618,16 +1621,6 @@ class BaseConstraint(ModelEntity):
16181621
pass
16191622

16201623

1621-
# FIXME: exists 2 times
1622-
@export
1623-
class RangeExpression(BaseConstraint):
1624-
_range: Range
1625-
1626-
@property
1627-
def Range(self):
1628-
return self._range
1629-
1630-
16311624
# FIXME: Is this used?
16321625
@export
16331626
class RangeAttribute(BaseConstraint):

pyVHDLModel/__init__.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,9 @@
3535
# ==============================================================================
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#
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"""
38+
An abstract VHDL language model.
39+
3840
:copyright: Copyright 2007-2021 Patrick Lehmann - Bötzingen, Germany
3941
:license: Apache License, Version 2.0
4042
"""
41-
__version__ = "0.8.1"
43+
__version__ = "0.10.5"

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