Skip to content

Commit 4a724b6

Browse files
authored
v0.27.1
2 parents df37970 + 9f49589 commit 4a724b6

File tree

3 files changed

+19
-4
lines changed

3 files changed

+19
-4
lines changed

pyVHDLModel/DesignUnit.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -615,13 +615,13 @@ def Library(self, library: 'Library') -> None:
615615

616616
def __str__(self) -> str:
617617
lib = self._library._identifier if self._library is not None else "%"
618-
ent = self._entity._identifier if self._entity is not None else "%"
618+
ent = self._entity._name._identifier if self._entity is not None else "%"
619619

620620
return f"Architecture: {lib}.{ent}({self._identifier})"
621621

622622
def __repr__(self) -> str:
623623
lib = self._library._identifier if self._library is not None else "%"
624-
ent = self._entity.Name._identifier if self._entity is not None else "%"
624+
ent = self._entity._name._identifier if self._entity is not None else "%"
625625

626626
return f"{lib}.{ent}({self._identifier})"
627627

pyVHDLModel/Exception.py

+13
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,9 @@
3535
The module ``Exceptions`` contains all structured errors that are raised by pyVHDLModel. Besides a default error
3636
message in english, each exception object contains one or multiple references to the exception's context.
3737
"""
38+
from sys import version_info
39+
from typing import List
40+
3841
from pyTooling.Decorators import export
3942

4043
from pyVHDLModel.Symbol import Symbol
@@ -44,6 +47,16 @@
4447
class VHDLModelException(Exception):
4548
"""Base-class for all exceptions (errors) raised by pyVHDLModel."""
4649

50+
# WORKAROUND: for Python <3.11
51+
# Implementing a dummy method for Python versions before
52+
__notes__: List[str]
53+
if version_info < (3, 11): # pragma: no cover
54+
def add_note(self, message: str):
55+
try:
56+
self.__notes__.append(message)
57+
except AttributeError:
58+
self.__notes__ = [message]
59+
4760

4861
@export
4962
class LibraryExistsInDesignError(VHDLModelException):

pyVHDLModel/__init__.py

+4-2
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@
4848
__email__ = "[email protected]"
4949
__copyright__ = "2016-2023, Patrick Lehmann"
5050
__license__ = "Apache License, Version 2.0"
51-
__version__ = "0.27.0"
51+
__version__ = "0.27.1"
5252

5353

5454
from enum import unique, Enum, Flag, auto
@@ -979,7 +979,9 @@ def LinkLibraryReferences(self) -> None:
979979
try:
980980
library = self._libraries[libraryIdentifier]
981981
except KeyError:
982-
raise VHDLModelException(f"Library '{librarySymbol.Name.Identifier}' referenced by library clause of design unit '{designUnit.Identifier}' doesn't exist in design.")
982+
ex = VHDLModelException(f"Library '{librarySymbol.Name.Identifier}' referenced by library clause of design unit '{designUnit.Identifier}' doesn't exist in design.")
983+
ex.add_note(f"""Known libraries: '{"', '".join(library for library in self._libraries)}'""")
984+
raise ex
983985

984986
librarySymbol.Library = library
985987
designUnit._referencedLibraries[libraryIdentifier] = library

0 commit comments

Comments
 (0)