v0.11.3

Author: Paebbels

.idea/pyVHDLModel.iml

@@ -3,6 +3,22 @@
 Dependency
 ##########
 
+.. |img-pyVHDLModel-lib-status| image:: https://img.shields.io/librariesio/release/pypi/pyVHDLModel
+   :alt: Libraries.io status for latest release
+   :height: 22
+   :target: https://libraries.io/github/Paebbels/pyVHDLModel
+.. |img-pyVHDLModel-req-status| image:: https://img.shields.io/requires/github/Paebbels/pyVHDLModel
+   :alt: Requires.io
+   :height: 22
+   :target: https://requires.io/github/Paebbels/pyVHDLModel/requirements/?branch=master
+
++------------------------------------------+------------------------------------------+
+| `Libraries.io <https://libraries.io/>`_  | `Requires.io <https://requires.io/>`_    |
++==========================================+==========================================+
+| |img-pyVHDLModel-lib-status|             | |img-pyVHDLModel-req-status|             |
++------------------------------------------+------------------------------------------+
+
+
 .. _dependency-package:
 
 pyVHDLModel Package

doc/Dependency.rst

@@ -220,7 +220,7 @@ Case Generate
      def SelectExpression(self) -> BaseExpression:
 
      @property
-     def Cases(self) -> List[ConcurrentCase]:
+     def Cases(self) -> List[GenerateCase]:
 
 
 

doc/LanguageModel/ConcurrentStatements.rst

@@ -37,7 +37,7 @@ def _LatestTagName():
 
 # The full version, including alpha/beta/rc tags
 version = "0.11"     # The short X.Y version.
-release = "0.11.2"   # The full version, including alpha/beta/rc tags.
+release = "0.11.3"   # The full version, including alpha/beta/rc tags.
 try:
 	if _IsUnderGitControl:
 		latestTagName = _LatestTagName()[1:]		# remove prefix "v"

doc/conf.py

@@ -43,7 +43,7 @@
 # load dependencies
 from pydecor.decorators import export
 
-from pyVHDLModel.VHDLModel import PrimaryUnit, ModelEntity
+from pyVHDLModel import ModelEntity, PrimaryUnit
 
 
 __all__ = []

pyVHDLModel/PSLModel.py

@@ -0,0 +1,43 @@
+# =============================================================================
+#             __     ___   _ ____  _     __  __           _      _
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|
+#  |_|    |___/
+# ==============================================================================
+# Authors:            Patrick Lehmann
+#
+# Python module:      An abstract VHDL language model.
+#
+# Description:
+# ------------------------------------
+#		TODO:
+#
+# License:
+# ==============================================================================
+# Copyright 2017-2021 Patrick Lehmann - Boetzingen, Germany
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# ==============================================================================
+#
+"""
+This module contains a document language model for VHDL.
+
+:copyright: Copyright 2007-2021 Patrick Lehmann - Bötzingen, Germany
+:license: Apache License, Version 2.0
+"""
+# load dependencies