diff --git a/Getting_Started/Vitis/Part2.md b/Getting_Started/Vitis/Part2.md index d656f9e957..a06c7c89ee 100644 --- a/Getting_Started/Vitis/Part2.md +++ b/Getting_Started/Vitis/Part2.md @@ -11,8 +11,6 @@ # Vitis Getting Started Tutorial -***Version: Vitis 2021.2*** - ## Part 2 : Installation and Configuration To develop and deploy applications with Vitis, you need to install the Vitis unified software environment, the Xilinx Runtime library (XRT) and the platform files specific to the acceleration card used in your project. @@ -74,15 +72,20 @@ The packages required for each platform can be found on the corresponding downlo ### Step 5 – Setup the environment to run Vitis -To configure the environment to run Vitis, run the following scripts which set up the environment to run in a specific command shell. +To configure the environment to run Vitis, run the following script which sets up the environment to run in a specific command shell. ```bash -source /Vitis/2021.2/settings64.sh -source /opt/xilinx/xrt/setup.sh +source /Vitis/2022.1/settings64.sh ``` *NOTE: .csh scripts are also provided but this tutorial assumes a bash shell is used.* +To configure XRT for Alveo Data Center accelerator cards run the following script. This is not required for Embedded platforms. + +```bash +source /opt/xilinx/xrt/setup.sh +``` + To specify the location of any Data-Center or Embedded platforms you have installed, set the following environment variable: ```bash @@ -114,4 +117,4 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx

+

Copyright© 2020–2022 Xilinx

diff --git a/Getting_Started/Vitis/Part3.md b/Getting_Started/Vitis/Part3.md index fb47499b52..2a508696c1 100644 --- a/Getting_Started/Vitis/Part3.md +++ b/Getting_Started/Vitis/Part3.md @@ -11,8 +11,6 @@ # Vitis Getting Started Tutorial -***Version: Vitis 2021.2*** - ## Part 3 : Review the Kernel Code and Host Application The example used in this tutorial is a trivial vector-add application. The simplicity of this example allows focusing on the key concepts of FPGA acceleration without being distracted by complicated algorithmic consideration. @@ -119,4 +117,4 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx

+

Copyright© 2020–2022 Xilinx

diff --git a/Getting_Started/Vitis/Part4-data_center.md b/Getting_Started/Vitis/Part4-data_center.md index f36e77bec5..a9a481bf14 100644 --- a/Getting_Started/Vitis/Part4-data_center.md +++ b/Getting_Started/Vitis/Part4-data_center.md @@ -11,8 +11,6 @@ # Vitis Getting Started Tutorial -***Version: Vitis 2021.2*** - ## Part 4 : Build and Run the Data Center Application In this fourth part of the Introduction to Vitis tutorial, you will compile and run the vector-add example using each of three build targets supported in the Vitis flow as described below. The overall flow is described in [Data Center Application Acceleration Flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Data-Center-Application-Acceleration-Development-Flow), and includes the image flow diagram shown below. From the image you can see the standard G++ compilation process for the host application, and the use of the Vitis compiler (`v++`) for building the Xilinx device binary (`xclbin`). These are the steps you will be working through in this lab. @@ -29,7 +27,7 @@ ### Setting up the environment -> IMPORTANT: This tutorial requires Vitis 2021.1 or later to run. +> IMPORTANT: This tutorial requires Vitis 2022.1 or later to run. *NOTE: The instructions provided below assume that you are running in a bash shell.* @@ -61,9 +59,9 @@ Then, after changing into the target build directory, enter the following comman ```bash g++ -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I${XILINX_XRT}/include/ -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ -emconfigutil --platform xilinx_u200_gen3x16_xdma_1_202110_1 --nd 1 -v++ -c -t sw_emu --platform xilinx_u200_gen3x16_xdma_1_202110_1 --config ../../src/u200.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo -v++ -l -t sw_emu --platform xilinx_u200_gen3x16_xdma_1_202110_1 --config ../../src/u200.cfg ./vadd.xo -o vadd.xclbin +emconfigutil --platform xilinx_u200_gen3x16_xdma_2_202110_1 --nd 1 +v++ -c -t sw_emu --platform xilinx_u200_gen3x16_xdma_2_202110_1 --config ../../src/u200.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo +v++ -l -t sw_emu --platform xilinx_u200_gen3x16_xdma_2_202110_1 --config ../../src/u200.cfg ./vadd.xo -o vadd.xclbin ``` Here is a brief explanation of each of these four commands: @@ -75,10 +73,9 @@ Here is a brief explanation of each of these four commands: The `-t` option of the `v++` command specifies the build target. Here it is set to `sw_emu` so we are building for software emulation. -Notice also the `--config` option which is used to specify the name of a configuration file containing additional options. Here we are using this configuration file to specify the name of the targeted platform and the mapping of kernel arguments to specific memory banks. +Notice also the `--config` option which is used to specify the name of a configuration file containing additional options. Here we are using this configuration file to specify the number of kernels and the mapping of kernel arguments to specific memory banks. ```bash -platform=xilinx_u200_gen3x16_xdma_1_202110_1 debug=1 save-temps=1 @@ -137,9 +134,9 @@ Then, after changing into the target build directory, enter the following comman ```bash g++ -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I${XILINX_XRT}/include/ -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ -emconfigutil --platform xilinx_u200_gen3x16_xdma_1_202110_1 --nd 1 -v++ -c -t hw_emu --platform xilinx_u200_gen3x16_xdma_1_202110_1 --config ../../src/u200.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo -v++ -l -t hw_emu --platform xilinx_u200_gen3x16_xdma_1_202110_1 --config ../../src/u200.cfg ./vadd.xo -o vadd.xclbin +emconfigutil --platform xilinx_u200_gen3x16_xdma_2_202110_1 --nd 1 +v++ -c -t hw_emu --platform xilinx_u200_gen3x16_xdma_2_202110_1 --config ../../src/u200.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo +v++ -l -t hw_emu --platform xilinx_u200_gen3x16_xdma_2_202110_1 --config ../../src/u200.cfg ./vadd.xo -o vadd.xclbin ``` Refer to *Targeting Software Emulation* for a brief explanation of these different commands. The only difference with the previous step is the `v++` target (`-t`) option which is changed from `sw_emu` to `hw_emu`. All other options remain the same. @@ -168,8 +165,8 @@ Then, after changing into the target build directory, enter the following comman ```bash g++ -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I${XILINX_XRT}/include/ -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ -v++ -c -t hw --platform xilinx_u200_gen3x16_xdma_1_202110_1 --config ../../src/u200.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo -v++ -l -t hw --platform xilinx_u200_gen3x16_xdma_1_202110_1 --config ../../src/u200.cfg ./vadd.xo -o vadd.xclbin +v++ -c -t hw --platform xilinx_u200_gen3x16_xdma_2_202110_1 --config ../../src/u200.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo +v++ -l -t hw --platform xilinx_u200_gen3x16_xdma_2_202110_1 --config ../../src/u200.cfg ./vadd.xo -o vadd.xclbin ``` To target Hardware, the `v++ -t` option is set to `hw` and the `emconfigutil` command is not needed, as you will be running on an actual hardware platform rather than an emulated platform. All other options remain identical. @@ -186,7 +183,7 @@ After the build completes you can run the application on a system with the Alveo You should see the same TEST PASSED message indicating that the run completed successfully. If you look in the u200/hw folder you will see some of the files that were created during this build and run process. Refer to *Targeting Software Emulation* for a brief explanation of the different files. -Congratulations!! You have just completed your first run of a Vitis accelerated application on the Alveo U200 card! There are additional [Vitis-Tutorials](https://github.com/Xilinx/Vitis-Tutorials) to work through to learn additional details of the Vitis tools, and [Vitis_Accel_Examples](https://github.com/Xilinx/Vitis_Accel_Examples/tree/2021.2) to use for examples of host application and kernel coding. +Congratulations!! You have just completed your first run of a Vitis accelerated application on the Alveo U200 card! There are additional [Vitis-Tutorials](https://github.com/Xilinx/Vitis-Tutorials) to work through to learn additional details of the Vitis tools, and [Vitis_Accel_Examples](https://github.com/Xilinx/Vitis_Accel_Examples/tree/2022.1) to use for examples of host application and kernel coding. ## Next Step @@ -205,4 +202,4 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx

+

Copyright© 2020–2022 Xilinx

diff --git a/Getting_Started/Vitis/Part4-embedded_platform.md b/Getting_Started/Vitis/Part4-embedded_platform.md index a8a757cdde..feb0d38d89 100644 --- a/Getting_Started/Vitis/Part4-embedded_platform.md +++ b/Getting_Started/Vitis/Part4-embedded_platform.md @@ -11,8 +11,6 @@ # Vitis Getting Started Tutorial -***Version: Vitis 2021.2*** - ## Part 4 : Build and Run the Embedded Processor Application In this fourth part of the Introduction to Vitis tutorial, you will compile and run the vector-add example using each of three build targets supported in the Vitis flow as described below. The overall flow is described in [Embedded Processor Application Acceleration Flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Embedded-Processor-Application-Acceleration-Development-Flow), and includes the image flow diagram shown below. From the image you can see the G++ cross-compiler for building the host application for the Arm processor, and the use of the Vitis compiler (`v++`) for building the Xilinx device binary (`xclbin`). These are the steps you will be working through in this lab. @@ -37,7 +35,6 @@ ```bash source /settings64.sh -source /setup.sh unset LD_LIBRARY_PATH ``` @@ -72,9 +69,9 @@ Then, after changing into the target build directory, enter the following comman ```bash $CXX -Wall -g -std=c++11 ../../src/host.cpp -o ./app.exe -I/usr/include/xrt -lOpenCL -lpthread -lrt -lstdc++ -v++ -c -t sw_emu --config ../../src/zcu102.cfg -k vadd -I../../src ../../src/vadd.cpp -o ./vadd.xo -v++ -l -t sw_emu --config ../../src/zcu102.cfg ./vadd.xo -o ./vadd.xclbin -v++ -p -t sw_emu --config ../../src/zcu102.cfg ./vadd.xclbin --package.out_dir ./package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file ./xrt.ini --package.sd_file ./app.exe --package.sd_file ./vadd.xclbin --package.sd_file ./run_sw_emu.sh +v++ -c -t sw_emu --platform xilinx_zcu102_base_202210_1 --config ../../src/zcu102.cfg -k vadd -I../../src ../../src/vadd.cpp -o ./vadd.xo +v++ -l -t sw_emu --platform xilinx_zcu102_base_202210_1 --config ../../src/zcu102.cfg ./vadd.xo -o ./vadd.xclbin +v++ -p -t sw_emu --platform xilinx_zcu102_base_202210_1 --config ../../src/zcu102.cfg ./vadd.xclbin --package.out_dir ./package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file ./xrt.ini --package.sd_file ./app.exe --package.sd_file ./vadd.xclbin --package.sd_file ./run_sw_emu.sh ``` Here is a brief explanation of each of these four commands: @@ -164,9 +161,9 @@ Then, after changing into the target build directory, enter the following comman ```bash $CXX -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I/usr/include/xrt -lOpenCL -lpthread -lrt -lstdc++ -v++ -c -t hw_emu --config ../../src/zcu102.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo -v++ -l -t hw_emu --config ../../src/zcu102.cfg ./vadd.xo -o vadd.xclbin -v++ -p -t hw_emu --config ../../src/zcu102.cfg ./vadd.xclbin --package.out_dir package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file xrt.ini --package.sd_file app.exe --package.sd_file vadd.xclbin --package.sd_file run_app.sh +v++ -c -t hw_emu --platform xilinx_zcu102_base_202210_1 --config ../../src/zcu102.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo +v++ -l -t hw_emu --platform xilinx_zcu102_base_202210_1 --config ../../src/zcu102.cfg ./vadd.xo -o vadd.xclbin +v++ -p -t hw_emu --platform xilinx_zcu102_base_202210_1 --config ../../src/zcu102.cfg ./vadd.xclbin --package.out_dir package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file xrt.ini --package.sd_file app.exe --package.sd_file vadd.xclbin --package.sd_file run_app.sh ``` Refer to *Targeting Software Emulation* for a brief explanation of these different commands. The only difference with the previous step is the `v++` target (`-t`) option which is changed from `sw_emu` to `hw_emu`. All other options remain the same. @@ -214,9 +211,9 @@ Then, after changing into the target build directory, enter the following comman ```bash $CXX -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I/usr/include/xrt -lOpenCL -lpthread -lrt -lstdc++ -O -v++ -c -t hw --config ../../src/zcu102.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo -v++ -l -t hw --config ../../src/zcu102.cfg ./vadd.xo -o vadd.xclbin -v++ -p -t hw --config ../../src/zcu102.cfg ./vadd.xclbin --package.out_dir package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file xrt.ini --package.sd_file app.exe --package.sd_file vadd.xclbin --package.sd_file run_app.sh +v++ -c -t hw --platform xilinx_zcu102_base_202210_1 --config ../../src/zcu102.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo +v++ -l -t hw --platform xilinx_zcu102_base_202210_1 --config ../../src/zcu102.cfg ./vadd.xo -o vadd.xclbin +v++ -p -t hw --platform xilinx_zcu102_base_202210_1 --config ../../src/zcu102.cfg ./vadd.xclbin --package.out_dir package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file xrt.ini --package.sd_file app.exe --package.sd_file vadd.xclbin --package.sd_file run_app.sh ``` To target Hardware, the `v++ -t` option is set to `hw` and the `emconfigutil` command is not needed, as you will be running on an actual hardware platform rather than an emulated platform. All other options remain identical. @@ -233,7 +230,7 @@ export XILINX_XRT=/usr You should see the same TEST PASSED message indicating that the run completed successfully. If you look in the zcu102/hw folder you will see some of the files that were created during this build and run process. Refer to *Targeting Software Emulation* for a brief explanation of the different files. -Congratulations!! You have just completed your first run of a Vitis accelerated application on the ZCU102 card! There are additional [Vitis-Tutorials](https://github.com/Xilinx/Vitis-Tutorials) to work through to learn additional details of the Vitis tools, and [Vitis_Accel_Examples](https://github.com/Xilinx/Vitis_Accel_Examples/tree/2021.2) to use for examples of host application and kernel coding. +Congratulations!! You have just completed your first run of a Vitis accelerated application on the ZCU102 card! There are additional [Vitis-Tutorials](https://github.com/Xilinx/Vitis-Tutorials) to work through to learn additional details of the Vitis tools, and [Vitis_Accel_Examples](https://github.com/Xilinx/Vitis_Accel_Examples/tree/2022.1) to use for examples of host application and kernel coding. ## Next Step @@ -252,4 +249,4 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx

+

Copyright© 2020–2022 Xilinx

diff --git a/Getting_Started/Vitis/Part5.md b/Getting_Started/Vitis/Part5.md index 891ef1f5b2..fbe38aebe4 100644 --- a/Getting_Started/Vitis/Part5.md +++ b/Getting_Started/Vitis/Part5.md @@ -11,8 +11,6 @@ # Vitis Getting Started Tutorial -***Version: Vitis 2021.2*** - ## Part 5 : Visualizing Results and Analyzing Reports Now that you have successfully built and run the vector-add example, now you can look at the results and reports generated along the way. This example is configured to generate build and run summaries for all three build targets (software emulation, hardware emulation and hardware). Any of these summary reports can be viewed and analyzed using the Vitis analyzer tool as described in [Using the Vitis Analyzer](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Using-the-Vitis-Analyzer). @@ -41,11 +39,10 @@ If you look into the directory where you ran the application, you will notice th *IMPORTANT: If you targeted the ZCU102 hardware, these files are stored on the SD card and must be copied back to your workstation to continue this lab. Refer to [Running Emulation on an Embedded Processor Platform](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Running-Emulation-on-an-Embedded-Processor-Platform) for more information.* -The generation of these files and reports is controlled by runtime options located in the `xrt.ini` file. This tutorial contains a pre-existing `xrt.ini` file which enables the generation of profile data and a timeline of execution with the following content: +The generation of these files and reports is controlled by runtime options located in the `xrt.ini` file. This tutorial contains a pre-existing `xrt.ini` file which enables the generation a timeline of execution, and the profile summary data, with the following content: ```bash [Debug] -opencl_summary=true opencl_trace=true ``` @@ -119,4 +116,4 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx

+

Copyright© 2020–2022 Xilinx

diff --git a/Getting_Started/Vitis/README.md b/Getting_Started/Vitis/README.md index 1c4ada8190..674c9df836 100644 --- a/Getting_Started/Vitis/README.md +++ b/Getting_Started/Vitis/README.md @@ -12,7 +12,7 @@ # Vitis™ Getting Started Tutorial -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** ![img](./images/vitis_101.png) @@ -109,4 +109,4 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx

+

Copyright© 2020–2022 Xilinx

diff --git a/Getting_Started/Vitis/example/u200/xrt.ini b/Getting_Started/Vitis/example/u200/xrt.ini index 95af010c98..f172573ef0 100644 --- a/Getting_Started/Vitis/example/u200/xrt.ini +++ b/Getting_Started/Vitis/example/u200/xrt.ini @@ -1,3 +1,2 @@ [Debug] -opencl_summary=true opencl_trace=true diff --git a/Getting_Started/Vitis/example/zcu102/xrt.ini b/Getting_Started/Vitis/example/zcu102/xrt.ini index 95af010c98..f172573ef0 100644 --- a/Getting_Started/Vitis/example/zcu102/xrt.ini +++ b/Getting_Started/Vitis/example/zcu102/xrt.ini @@ -1,3 +1,2 @@ [Debug] -opencl_summary=true opencl_trace=true diff --git a/Getting_Started/Vitis_HLS/README.md b/Getting_Started/Vitis_HLS/README.md index e771967f45..1f23743da4 100644 --- a/Getting_Started/Vitis_HLS/README.md +++ b/Getting_Started/Vitis_HLS/README.md @@ -1,8 +1,8 @@ - +
+ +

Vitis™ Application Acceleration Tutorials

- See 2020.2 Tutorials -
@@ -11,7 +11,7 @@
- +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
diff --git a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/cosim.md b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/cosim.md index 094cc62a05..d99f43812a 100644 --- a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/cosim.md +++ b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/cosim.md @@ -1,6 +1,6 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
diff --git a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/csim.md b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/csim.md index 393db1d409..3f53e14ff4 100644 --- a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/csim.md +++ b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/csim.md @@ -1,6 +1,6 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
diff --git a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/csynth.md b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/csynth.md index 9ec077b32d..994b9643b5 100644 --- a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/csynth.md +++ b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/csynth.md @@ -1,6 +1,6 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
diff --git a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/design.md b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/design.md index a160c55710..1865c9f0f6 100644 --- a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/design.md +++ b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/design.md @@ -1,6 +1,6 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
- > **In this section...** We describe the full design structure (testbench and accelerated function) and discuss the compiler hints (pragmas) applied. diff --git a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/export.md b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/export.md index ab2a24c867..f83905f199 100644 --- a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/export.md +++ b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/export.md @@ -1,6 +1,6 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
diff --git a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/project.md b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/project.md index 41842f34bc..f141230424 100644 --- a/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/project.md +++ b/Hardware_Acceleration/Design_Tutorials/04-traveling-salesperson/project.md @@ -1,6 +1,6 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/01-Workflows/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/01-Workflows/README.md index 59de1b2977..a5300b65c0 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/01-Workflows/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/01-Workflows/README.md @@ -1,7 +1,7 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/02-System_Setup/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/02-System_Setup/README.md index 9532e1a3be..a84c8f5a9b 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/02-System_Setup/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/02-System_Setup/README.md @@ -1,7 +1,7 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
@@ -25,7 +25,7 @@ The [Vitis Unified Software Development Platform](https://www.xilinx.com/product

For this tutorial, you need to set below environment variable to your Terminal of Nimbix Desktop before start to launch Vitis or run Makefile command we provided with source code.

-
 export PATH=/opt/xilinx/Vivado/2021.2/tps/lnx64/gcc-6.2.0/bin:$PATH
+
 export PATH=/opt/xilinx/Vivado/2022.1/tps/lnx64/gcc-6.2.0/bin:$PATH
@@ -44,7 +44,7 @@ To install Alveo U50 accelerator card on your server, follow the instructions in

For this tutorial, you need to set below environment variable to your Terminal of Nimbix Desktop before start to launch Vitis or run Makefile command we provided with source code.

- 
export PATH=/opt/xilinx/Vivado/2021.2/tps/lnx64/gcc-6.2.0/bin:$PATH
+ 
export PATH=/opt/xilinx/Vivado/2022.1/tps/lnx64/gcc-6.2.0/bin:$PATH
@@ -52,7 +52,7 @@ To install Alveo U50 accelerator card on your server, follow the instructions in To configure the environment to run the Vitis software platform, run the following scripts, which set up the environment to run in a specific command shell. ~~~ #setup XILINX_VITIS and XILINX_VIVADO variables -source /Vitis/2021.2/settings64.sh +source /Vitis/2022.1/settings64.sh #setup XILINX_XRT source /opt/xilinx/xrt/setup.sh ~~~ @@ -109,4 +109,4 @@ INFO: All cards validated successfully. Please proceed to [**Section 3**](../03-Algorithm_Acceleration/README.md). -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/README.md index d81e087895..0245613812 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/README.md @@ -1,7 +1,7 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
@@ -32,4 +32,4 @@ _Instructions in local readme files for each module_ + Use Vitis HLS to confirm the new micro-architecture created by dataflow + Generate the binary (xclbin) to program the card and measure the actual performance -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/README.md index af47fa28ef..90dce27ca1 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/README.md @@ -2,4 +2,4 @@ Visit the cpu_src and then move to the module prefixed Local README.md files provide instructions... -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/cpu_src/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/cpu_src/README.md index be8699b4d6..ecfd54c41c 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/cpu_src/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/cpu_src/README.md @@ -1,7 +1,7 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
@@ -21,7 +21,7 @@ This algorithm has a serial complexity O(n3). [_More information on wikipedia..._](https://en.wikipedia.org/wiki/Cholesky_decomposition) Note that this solver is included as part the official Vitis accelerated libraries, here is a link to its documentation: -https://xilinx.github.io/Vitis_Libraries/solver/2021.2/guide_L2/L2_api.html#potrf +https://xilinx.github.io/Vitis_Libraries/solver/2022.1/guide_L2/L2_api.html#potrf For our purpose, we will start with a simple description implemented in C++ and explain how to adapt it for acceleration with an Alveo U50 card. @@ -46,4 +46,4 @@ Study the code to check how it implements the Cholesky algorithm. Continue to [**module 1**](../module1_baseline/README.md) to build and run a baseline version with Vitis. -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module1_baseline/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module1_baseline/README.md index 1bd2475239..87d4ff7e77 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module1_baseline/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module1_baseline/README.md @@ -1,7 +1,7 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
@@ -244,4 +244,4 @@ You can now proceed to [**module 2**](../module2_pipeline/README.md). *** -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module1_baseline/xrt.ini b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module1_baseline/xrt.ini index fc8dc8a770..dd5bc68696 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module1_baseline/xrt.ini +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module1_baseline/xrt.ini @@ -1,6 +1,5 @@ [Debug] -opencl_summary=true opencl_trace=true -data_transfer_trace=off +device_trace=off stall_trace=off app_debug=false diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module2_pipeline/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module2_pipeline/README.md index 688f89f1c4..5f9efb09e3 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module2_pipeline/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module2_pipeline/README.md @@ -1,7 +1,7 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
@@ -83,4 +83,4 @@ For example, a pipelined for-loop with 100 accesses and max_read_burst_length or You can now continue to [module 3](../module3_datatype/README.md) or run this version of the design to verify it behaves similarly to module 1. -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module2_pipeline/xrt.ini b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module2_pipeline/xrt.ini index fc8dc8a770..dd5bc68696 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module2_pipeline/xrt.ini +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module2_pipeline/xrt.ini @@ -1,6 +1,5 @@ [Debug] -opencl_summary=true opencl_trace=true -data_transfer_trace=off +device_trace=off stall_trace=off app_debug=false diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module3_datatype/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module3_datatype/README.md index 34403b3054..a64c7b01d1 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module3_datatype/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module3_datatype/README.md @@ -1,7 +1,7 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
@@ -43,4 +43,4 @@ Users can often get better performance by scaling down the precision of their da Proceed to [**module 4**](../module4_dataflow/README.md). -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module3_datatype/xrt.ini b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module3_datatype/xrt.ini index fc8dc8a770..dd5bc68696 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module3_datatype/xrt.ini +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module3_datatype/xrt.ini @@ -1,6 +1,5 @@ [Debug] -opencl_summary=true opencl_trace=true -data_transfer_trace=off +device_trace=off stall_trace=off app_debug=false diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module4_dataflow/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module4_dataflow/README.md index 96027c5ba5..bf10370b0f 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module4_dataflow/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module4_dataflow/README.md @@ -1,7 +1,7 @@ - +
-

Vitis Hardware Acceleration

- See Vitis™ Development Environment on xilinx.com
 +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com
@@ -125,4 +125,4 @@ Actual results comparing the runs for all modules including execution on the CPU This concludes this introductory tutorial on Vitis Hardware Acceleration. [Click here](../../../../README.md) to find more Vitis design optimization tutorials. -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module4_dataflow/xrt.ini b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module4_dataflow/xrt.ini index fc8dc8a770..dd5bc68696 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module4_dataflow/xrt.ini +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/03-Algorithm_Acceleration/docs/module4_dataflow/xrt.ini @@ -1,6 +1,5 @@ [Debug] -opencl_summary=true opencl_trace=true -data_transfer_trace=off +device_trace=off stall_trace=off app_debug=false diff --git a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/README.md b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/README.md index c1c3c8610c..a5d0b671e7 100644 --- a/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/README.md +++ b/Hardware_Acceleration/Design_Tutorials/06-cholesky-accel/README.md @@ -1,18 +1,15 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
### Vitis Hardware Acceleration on Cholesky Algorithm -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** This tutorial is divided in 3 sections. @@ -58,7 +55,7 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx
XD018

+

Copyright© 2020–2022 Xilinx
XD018

diff --git a/Hardware_Acceleration/Design_Tutorials/07-host-code-opt/README.md b/Hardware_Acceleration/Design_Tutorials/07-host-code-opt/README.md index e3ec1d0226..ad02880f59 100644 --- a/Hardware_Acceleration/Design_Tutorials/07-host-code-opt/README.md +++ b/Hardware_Acceleration/Design_Tutorials/07-host-code-opt/README.md @@ -1,18 +1,14 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Vitis™ Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
- # Host Code Optimization -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** ## Introduction @@ -39,7 +35,7 @@ The following sections focus on the following specific host code optimization co This tutorial uses: * BASH Linux shell commands -* 2021.2 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_1_202110_1* platform. +* 2022.1 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_2_202110_1* platform. If necessary, it can be easily ported to other versions and platforms. >**IMPORTANT:** @@ -71,7 +67,7 @@ Although some host code optimizations perform well with the hardware emulation, Run the following makefile command to compile the kernel to the specified accelerator card. ``` -make TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_1_202110_1 xclbin +make TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_2_202110_1 xclbin ``` >**NOTE:** This build process can take several hours, but the kernel compilation must be completed before you can analyze the impact of optimizations on the host code performance. @@ -161,33 +157,32 @@ In this case, the code schedules all the buffers and lets them execute. Only at 1. Compile and run the host code (`srcPipeline/host.cpp`) using the following command. ``` - make TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_1_202110_1 LAB=pipeline + make TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_2_202110_1 LAB=pipeline ``` Compared to the kernel compilation time, this build step takes very little time. 2. You are now ready to run the application. - The runtime data is generated by the host program due to settings specified in the `xrt.ini` file, as described in [Enabling Profiling in Your Application](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/profilingapplication.html#vfc1586356138757). This file is found at `./reference-files/auxFiles/xrt.ini`, and is copied to the `runPipeline` directory by the `make run` command. + The runtime data is generated by the host program due to settings specified in the `xrt.ini` file, as described in [Enabling Profiling in Your Application](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Enabling-Profiling-in-Your-Application). This file is found at `./reference-files/auxFiles/xrt.ini`, and is copied to the `runPipeline` directory by the `make run` command. The `xrt.ini` file contains the following settings: ``` [Debug] - opencl_summary=true opencl_trace=true - data_transfer_trace=coarse + device_trace=coarse ``` Use the following command to run the application. ``` - make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_1_202110_1 LAB=pipeline + make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_2_202110_1 LAB=pipeline ``` After the run completes, open the Application Timeline using the Vitis analyzer, then select the Application Timeline located in left side panel. ``` - vitis_analyzer runPipeline/pass.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin.run_summary + vitis_analyzer runPipeline/pass.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin.run_summary ``` The Application Timeline view illustrates the full run of the executable. The three main sections of the timeline are: @@ -218,8 +213,8 @@ In this case, the code schedules all the buffers and lets them execute. Only at 5. Recompile the application, rerun the program, and review the run_summary in Vitis analyze: ``` - make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_1_202110_1 LAB=pipeline - vitis_analyzer pipeline/pass.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin.run_summary + make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_2_202110_1 LAB=pipeline + vitis_analyzer pipeline/pass.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin.run_summary ``` If you zoom in on the Application Timeline, and click any kernel enqueue, you should see results similar to the following figure. @@ -271,13 +266,13 @@ To alleviate these issues, the OpenCL framework provides two methods of synchron 2. Compile and execute the `sync_host.cpp` code. ``` - make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_1_202110_1 LAB=sync + make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_2_202110_1 LAB=sync ``` 3. After the run completes, open the Application Timeline using the Vitis analyzer, then click the Application Timeline located at left side panel. ``` - vitis_analyzer sync/pass.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin.run_summary + vitis_analyzer sync/pass.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin.run_summary ``` If you zoom in on the Application Timeline, an image is displayed similar to the following figure. @@ -307,8 +302,8 @@ To alleviate these issues, the OpenCL framework provides two methods of synchron 5. Recompile the application, rerun the program, and review the run_summary in Vitis analyze: ``` - make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_1_202110_1 LAB=sync - vitis_analyzer sync/pass.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin.run_summary + make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_2_202110_1 LAB=sync + vitis_analyzer sync/pass.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin.run_summary ``` If you zoom in on the Application Timeline, an image is displayed similar to the following figure. @@ -349,7 +344,7 @@ A second command line option (`SIZE=`) has also been added to specify the buffer 1. Compile and run the host code. ``` - make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_1_202110_1 SIZE=14 LAB=buf + make run TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_2_202110_1 SIZE=14 LAB=buf ``` The argument `SIZE` is used as a second argument to the host executable. @@ -360,14 +355,14 @@ A second command line option (`SIZE=`) has also been added to specify the buffer 3. After the run completes, open the Application Timeline using the Vitis analyzer, then click the Application Timeline located at left side panel. ``` - vitis_analyzer buf/pass.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin.run_summary + vitis_analyzer buf/pass.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin.run_summary ``` Examine the tmeline to review the operation. 4. To ease the sweeping of different buffer sizes, an additional makefile target was created, wich can be run using the following command. ``` - make TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_1_202110_1 bufRunSweep + make TARGET=hw DEVICE=xilinx_u200_gen3x16_xdma_2_202110_1 bufRunSweep ``` >**NOTE**: The sweeping script (`auxFiles/run.py`) requires a Python installation, which is available in most systems. @@ -409,4 +404,4 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx
XD018

+

Copyright© 2020–2022 Xilinx
XD018

diff --git a/Hardware_Acceleration/Design_Tutorials/07-host-code-opt/reference-files/auxFiles/xrt.ini b/Hardware_Acceleration/Design_Tutorials/07-host-code-opt/reference-files/auxFiles/xrt.ini index d4eb3b757f..038baef502 100644 --- a/Hardware_Acceleration/Design_Tutorials/07-host-code-opt/reference-files/auxFiles/xrt.ini +++ b/Hardware_Acceleration/Design_Tutorials/07-host-code-opt/reference-files/auxFiles/xrt.ini @@ -1,5 +1,4 @@ [Debug] -opencl_summary=true opencl_trace=true -data_transfer_trace=coarse +device_trace=coarse stall_trace=all diff --git a/Hardware_Acceleration/Design_Tutorials/README.md b/Hardware_Acceleration/Design_Tutorials/README.md index 69b2bfa13a..d22965a800 100644 --- a/Hardware_Acceleration/Design_Tutorials/README.md +++ b/Hardware_Acceleration/Design_Tutorials/README.md @@ -48,4 +48,4 @@ The methodology for developing optimized accelerated applications is comprised o -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/README.md b/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/README.md index c950dd8bc2..9ba774a452 100644 --- a/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/README.md +++ b/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/README.md @@ -1,21 +1,18 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
# Getting Started with RTL Kernels -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** ## Tutorial Overview -In the Vitis application acceleration development flow, as explained in [Kernel Properties](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/appdev.html#fiv1568160307462), RTL kernels can be either XRT-managed kernels adhering to XRT requirements of the `ap_ctrl_chain` or `ap_ctrl_hs` control protocols for execution control, or can be user-managed kernels that do not meet this standard but rather implement any number of user-defined control schemes specified in the RTL design. You can use an existing execution mechanism in an existing RTL design, or design your RTL to support the XRT control scheme. +In the Vitis application acceleration development flow, as explained in [Kernel Properties](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/PL-Kernel-Properties), RTL kernels can be either XRT-managed kernels adhering to XRT requirements of the `ap_ctrl_chain` or `ap_ctrl_hs` control protocols for execution control, or can be user-managed kernels that do not meet this standard but rather implement any number of user-defined control schemes specified in the RTL design. You can use an existing execution mechanism in an existing RTL design, or design your RTL to support the XRT control scheme. In this tutorial you will examine the process of packaging an existing RTL design with a user-managed control scheme into an RTL kernel, and review the host application requirements to integrate that kernel into your accelerated application. @@ -34,12 +31,12 @@ Using these reference files, the tutorial guides you through the process of buil The labs in this tutorial use: * BASH Linux shell commands -* 2021.2 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_1_202110_1* platform. +* 2022.1 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_2_202110_1* platform. * If necessary, the tutorial can be easily extended to other versions and platforms. >**IMPORTANT:** > -> * Before running any of the examples, make sure you have the Vitis core development kit installed as described in [Installation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/acceleration_installation.html#vhc1571429852245). +> * Before running any of the examples, make sure you have the Vitis core development kit installed as described in [Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation). >* If you run applications on Xilinx® Alveo™ Data Center accelerator cards, ensure the card and software drivers have been correctly installed by following the instructions on the [Alveo Portfolio page](https://www.xilinx.com/products/boards-and-kits/alveo.html). ### Accessing the Tutorial Reference Files @@ -49,7 +46,7 @@ The labs in this tutorial use: ## Requirements for Using an RTL Design as an RTL Kernel -To use an RTL kernel within the Vitis IDE, it must meet both the Vitis core development kit execution model and the hardware interface requirements as described in [RTL Kernels](https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vitis+doc;d=devrtlkernel.html) in the Vitis Application Acceleration Development Flow documentation (UG1393). +To use an RTL kernel within the Vitis IDE, it must meet both the Vitis core development kit execution model and the hardware interface requirements as described in [RTL Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/RTL-Kernels) in the Vitis Application Acceleration Development Flow documentation (UG1393). RTL kernels can use the same software interface and execution model as C/C++ software functions. They are seen by the host application as functions with a void return value, scalar and pointer arguments. @@ -89,4 +86,4 @@ This tutorial demonstrates how to package RTL IPs as Vitis kernels (`.xo`), and

Return to Main Page

-

Copyright© 2021 Xilinx

+

Copyright© 2021-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/host-code.md b/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/host-code.md index 77fd22df51..e40530ac89 100644 --- a/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/host-code.md +++ b/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/host-code.md @@ -1,11 +1,8 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
@@ -13,7 +10,7 @@ User-managed RTL kernels are only supported in host applications written with the XRT native API, as described in the [XRT documentation](https://xilinx.github.io/XRT/master/html/xrt_native_apis.html). The XRT native API provides a rich set of class objects and functions for XRT-managed kernels, as discussed in the *XRT Native API Host Application* tutorial, and for user-managed kernels as described here. -Open the `reference-files/src/host/user-host.cpp` file to examine its content and structure. As decribed in [Host Programming](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/devhostapp.html#vpy1519742402284) in the Vitis Application Acceleration Development Flow Documentation (UG1393), there are several key steps the host application must follow: +Open the `reference-files/src/host/user-host.cpp` file to examine its content and structure. As decribed in [Host Programming](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Host-Programming) in the Vitis Application Acceleration Development Flow Documentation (UG1393), there are several key steps the host application must follow: 1. Specifying the accelerator device ID and loading the `.xclbin` 2. Setting up the kernel and kernel arguments @@ -37,7 +34,7 @@ This tutorial will walk you through each of these, and discuss the requirements The XRT native API requires some `#include` statements to support the various class objects and functions of the different elements of the system. In the code sample above you can see the inclusion of header files for the Xilinx device, the device binary (`.xclbin`), the buffer objects (`xrt_bo`), and the user-managed kernel (`xrt_ip`). This last is an important difference in the XRT native API when working with XRT-managed kernels and user-managed kernels. -XRT managed kernels (`xrt::kernel`) meet specific requirements of control protocols and interfaces, as described in [Requirements of an RTL Kernel](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/devrtlkernel.html#qbh1504034323531) and as such have a richer feature set in the XRT API. User-managed kernels are a bit more unstructured, and so are represented in the IP class with limited features. +XRT managed kernels (`xrt::kernel`) meet specific requirements of control protocols and interfaces, as described in [Requirements of an RTL Kernel](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Requirements-of-an-RTL-Kernel) and as such have a richer feature set in the XRT API. User-managed kernels are a bit more unstructured, and so are represented in the IP class with limited features. ## Specifying the Device ID and Loading the XCLBIN @@ -187,5 +184,5 @@ Now you have created the RTL Kernel (`.xo`) file from a Vivado IP, and examined

Return to Main Page — Return to Start of this Tutorial

-

Copyright© 2021 Xilinx

+

Copyright© 2021-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/package_ip.md b/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/package_ip.md index cb0adde9fe..8b070d09ab 100644 --- a/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/package_ip.md +++ b/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/package_ip.md @@ -1,21 +1,16 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
# Package IP/Package XO Flow -***Version: Vitis 2021.2*** - -The process described in this lab follows the Package IP flow as described in the [RTL Kernel Development Flow](https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vitis+doc;d=devrtlkernel.html;a=rzv1504034325561) in the Vitis Application Acceleration Development Flow documentation (UG1393). +The process described in this lab follows the Package IP flow as described in the [RTL Kernel Development Flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/RTL-Kernel-Development-Flow) in the Vitis Application Acceleration Development Flow documentation (UG1393). ->**IMPORTANT:** Before running the tutorial commands, you must set up the tool environment by running the following commands, as described in [Setting up the Vitis Environment](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/settingupvitisenvironment.html#zks1565446519267). +>**IMPORTANT:** Before running the tutorial commands, you must set up the tool environment by running the following commands, as described in [Setting up the Vitis Environment](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Setting-Up-the-Vitis-Environment). > > ```bash > #setup Xilinx Vitis tools. XILINX_VITIS and XILINX_VIVADO will be set in this step. @@ -103,7 +98,7 @@ With the files added to your project, you can package the IP for use as a kernel ![Package for Vitis](images/control_protocol.png) - Enabling the **Package for Vitis** checkbox lets you specify the **Control protocol** for the RTL kernel. The default is `ap_ctrl_hs`, but other protocols such as `user_managed` and `ap_ctrl_chain` are also suported as described in [Software Controllable Kernels](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/appdev.html#pto1621516421839). + Enabling the **Package for Vitis** checkbox lets you specify the **Control protocol** for the RTL kernel. The default is `ap_ctrl_hs`, but other protocols such as `user_managed` and `ap_ctrl_chain` are also suported as described in [Software Controllable Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/SW-Controllable-Kernels). 3. Select `user_managed` for this tutorial. The tool sets required properties for the Vitis kernel. @@ -212,5 +207,5 @@ Next, you will examine the [Host Application Coding](./host-code.md) required to

Return to Main Page — Return to Start of this Tutorial

-

Copyright© 2021 Xilinx

+

Copyright© 2021-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/using_the_rtl_kernel.md b/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/using_the_rtl_kernel.md index d443cdb313..5c8f57dc8e 100644 --- a/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/using_the_rtl_kernel.md +++ b/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow/using_the_rtl_kernel.md @@ -1,11 +1,8 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
@@ -30,7 +27,7 @@ The New Vitis Application Project window opens. 4. The New Application Project wizard is displayed, with the overview page showing a brief overview of the process. Click **Next**. -5. The Plaform page is displayed. Select `xilinx_u200_gen3x16_xdma_1_202110_1`, and then click **Next** to proceed. +5. The Plaform page is displayed. Select `xilinx_u200_gen3x16_xdma_2_202110_1`, and then click **Next** to proceed. ![Platform page](images/rtl_kernel-platform_page.png) @@ -74,7 +71,7 @@ The New Vitis Application Project window opens. 4. The New Application Project wizard is displayed, with the overview page showing a brief overview of the process. Click **Next**. -5. The Plaform page is displayed. Select `xilinx_u200_gen3x16_xdma_1_202110_1`, and then click **Next** to proceed. +5. The Plaform page is displayed. Select `xilinx_u200_gen3x16_xdma_2_202110_1`, and then click **Next** to proceed. ![Platform page](images/rtl_kernel-platform_page.png) @@ -179,4 +176,4 @@ In this tutorial you have used the **Package IP/Package_XO** flow to create a us

Return to Getting Started Pathway — Return to Start of Tutorial

-

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/02-mixing-c-rtl-kernels/README.md b/Hardware_Acceleration/Feature_Tutorials/02-mixing-c-rtl-kernels/README.md index aef1901ed1..7a9cb34ac8 100644 --- a/Hardware_Acceleration/Feature_Tutorials/02-mixing-c-rtl-kernels/README.md +++ b/Hardware_Acceleration/Feature_Tutorials/02-mixing-c-rtl-kernels/README.md @@ -1,17 +1,14 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
# Mixing C++ and RTL Kernels -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** ## Introduction @@ -35,7 +32,7 @@ The host code and C++ kernel code are supplied. The RTL code will be generated u This tutorial uses: - BASH Linux shell commands. -- 2021.2 Vitis core development release and the *xilinx_u200_gen3x16_xdma_1_202110_1* platform. If necessary, it can be easily extended to other versions and platforms. +- 2021.2 Vitis core development release and the *xilinx_u200_gen3x16_xdma_2_202110_1* platform. If necessary, it can be easily extended to other versions and platforms. >**IMPORTANT:** > @@ -46,7 +43,7 @@ Before running any of the examples, ensure you have set up the Vitis core develo ```bash #setup Xilinx Vitis tools, XILINX_VITIS and XILINX_VIVADO will be set in this step. source /settings64.sh. for example: - source /opt/Xilinx/Vitis/2021.2/settings64.sh + source /opt/Xilinx/Vitis/2022.1/settings64.sh #Setup runtime. XILINX_XRT will be set in this step source /opt/xilinx/xrt/setup.sh ``` @@ -148,7 +145,7 @@ To run software emulation on the design, set the XCL_EMULATION_MODE environment ```bash export XCL_EMULATION_MODE=sw_emu - ./host krnl_vadd.sw_emu.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin + ./host krnl_vadd.sw_emu.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin ``` When the application successfully completes, the following message is displayed in the Console window. @@ -183,7 +180,7 @@ make all TARGET=sw_emu LAB=run1 export XCL_EMULATION_MODE=sw_emu # Run software emulation -./host krnl_vadd.sw_emu.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin +./host krnl_vadd.sw_emu.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin # View Application Timeline Trace in Vitis Analyzer vitis_analyzer xclbin.run_summary @@ -207,7 +204,7 @@ You will generate the RTL-based kernel by quickly going through the RTL Kernel W 2. Select **./mixing-c-rtl-kernels/workspace** as the workspace directory, and click **Launch**. 3. From the `Welcome` screen select **Create Application Project** to open the `New Project` wizard. 4. The first page displays a summary of the process. Click **Next** to proceed. -5. From the `Platform` page select the **xilinx_u200_gen3x16_xdma_1_202110_1** platform and click **Next**. +5. From the `Platform` page select the **xilinx_u200_gen3x16_xdma_2_202110_1** platform and click **Next**. 6. From the `Application Project Details` page, name your project `rtl_project` and click **Next**. 7. Under SW Acceleration Templates, select **Empty Application**, and click **Finish**. This creates a Vitis IDE project. @@ -301,7 +298,7 @@ With the RTL-based kernel added and host code updated, build the application, ta ```bash export XCL_EMULATION_MODE=hw_emu - ./host krnl_vadd.hw_emu.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin + ./host krnl_vadd.hw_emu.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin ``` 5. View the **Application Timeline** report in the Vitis analyzer. @@ -328,10 +325,10 @@ Because a CPP emulation file was packaged with the RTL Kernel (through the RTL W export XCL_EMULATION_MODE=sw_emu # Run software emulation -./host krnl_vadd.sw_emu.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin +./host krnl_vadd.sw_emu.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin # Open Vitis analyzer and view the timeline waveform -vitis_analyzer xclbin.run_summary +vitis_analyzer xrt.run_summary ``` ## Next Steps @@ -341,4 +338,4 @@ With the understanding that Vitis compiler can use kernels from a variety of bui

Return to Main Page

-

Copyright© 2021 Xilinx

+

Copyright© 2021-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/02-mixing-c-rtl-kernels/reference-files/xrt.ini b/Hardware_Acceleration/Feature_Tutorials/02-mixing-c-rtl-kernels/reference-files/xrt.ini index 7b3074a21c..af4c35cd23 100644 --- a/Hardware_Acceleration/Feature_Tutorials/02-mixing-c-rtl-kernels/reference-files/xrt.ini +++ b/Hardware_Acceleration/Feature_Tutorials/02-mixing-c-rtl-kernels/reference-files/xrt.ini @@ -1,4 +1,3 @@ [Debug] -opencl_summary=true opencl_trace=true -data_transfer_trace=fine +device_trace=fine diff --git a/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/README.md b/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/README.md index 3bfcbf64f1..a567503b8e 100755 --- a/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/README.md +++ b/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/README.md @@ -1,17 +1,14 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
# Vitis HLS Analysis and Optimization -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** ## Introduction @@ -24,11 +21,11 @@ The aim of this tutorial is to give the user an overview of the techniques avail The labs in this tutorial use: * BASH Linux shell commands. -* 2020.2 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_1_202110_1* platform. If necessary, it can be easily ported to other versions and platforms. +* 2022.1 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_2_202110_1* platform. If necessary, it can be easily ported to other versions and platforms. >**IMPORTANT:** > -> * Before running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/vitis_embedded_installation.html#tlp1602134446371) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). +> * Before running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). >* If you run applications on the Xilinx® Alveo™ Data Center accelerator cards, ensure the card and software drivers have been correctly installed by following the instructions To complete installation, follow the instructions on the [Alveo Product Documentation tab](https://www.xilinx.com/products/boards-and-kits/alveo.html). ## Accessing the Tutorial Reference Files @@ -48,4 +45,4 @@ Complete the labs in the following order:

Return to Main Page — Return to Getting Started Pathway


-

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/dataflow_viewer.md b/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/dataflow_viewer.md index 470f4f00cb..df58f4f7a1 100755 --- a/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/dataflow_viewer.md +++ b/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/dataflow_viewer.md @@ -1,12 +1,8 @@ - - - - - - +

2021.1 Vitis™ Application Acceleration Tutorials

- See 2021.1 Vitis Application Acceleration Development Flow Tutorials -

Vitis HLS Analysis and Optimization

-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
@@ -14,7 +10,7 @@ The DATAFLOW optimization tries to create task-level parallelism between the various functions in the code on top of the loop-level parallelism where possible. The optimization is done in two parts - first, the compiler infers the parallel tasks and sets up the communication channels and the associated control; second, after the generated RTL design is simulated, you can analyze the performance of the DATAFLOW optimization. Due to this fact, the Dataflow viewer lets you see the dataflow structure inferred by the tool, inspect the channels (FIFO/PIPO), and examine the effect of channel depth on performance. Performance data is then back-annotated to the Dataflow viewer from the co-simulation results. The Dataflow viewer also displays a representation of the dataflow graph structure, showing the different processes and the underlying producer-consumer connections. -**Tip:** You must apply the DATAFLOW pragma or directive to your design for the Dataflow viewer to be populated. You can apply dataflow to the top-level function, or specify regions of a function, or loops. For more information, refer to [set_directive_dataflow](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/optdirectives.html#rdd1585343102486) in the Vitis HLS flow of the Vitis Unified Software Platform documentation (UG1416). +**Tip:** You must apply the DATAFLOW pragma or directive to your design for the Dataflow viewer to be populated. You can apply dataflow to the top-level function, or specify regions of a function, or loops. For more information, refer to [set_directive_dataflow](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/set_directive_dataflow) in the Vitis HLS flow of the Vitis Unified Software Platform documentation (UG1416). ## Taking the tour @@ -90,7 +86,7 @@ It is important to understand that the dataflow optimization is a dynamic optimi ### Viewing the Dataflow Graph after RTL co-simulation -After synthesis, you must run co-simulation. For more information, refer to [C/RTL Co-Simulation in Vitis HLS](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/cosimulationinvitishls.html#fwf1584724080811) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416). +After synthesis, you must run co-simulation. For more information, refer to [C/RTL Co-Simulation in Vitis HLS](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/C/RTL-Co-Simulation-in-Vitis-HLS) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416). 1. From the menu, select the **Solution > Run C/RTL Co-Simulation** command. The Co-simulation dialog box displays as shown in the figure below. @@ -112,7 +108,7 @@ After synthesis, you must run co-simulation. For more information, refer to [C/R ![Open Dataflow Viewer](./images/dataflow_graph.png) - After running C/RTL co-simulation, the elements of the graph are filled out with performance data, and the Process and Channel tables beneath the graph are also filled out (as shown below). Without the performance data provided by RTL co-simulation, the graph and tables will have NA values to reflect the missing values. For more information, refer to [Dataflow Viewer](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/analyzingresultssynthesis.html#twx1584322463297) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416). + After running C/RTL co-simulation, the elements of the graph are filled out with performance data, and the Process and Channel tables beneath the graph are also filled out (as shown below). Without the performance data provided by RTL co-simulation, the graph and tables will have NA values to reflect the missing values. For more information, refer to [Dataflow Viewer](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Dataflow-Viewer) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416). ![Process Table](./images/process_table.png) @@ -182,4 +178,4 @@ To easily explain how the dataflow optimization executes the functions inside th

Return to Getting Started Pathway — Return to Start of Tutorial

-

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/fifo_sizing_and_deadlocks.md b/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/fifo_sizing_and_deadlocks.md index 09f4254d15..704bf18744 100755 --- a/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/fifo_sizing_and_deadlocks.md +++ b/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/fifo_sizing_and_deadlocks.md @@ -1,12 +1,8 @@ - - - - - - +

2021.1 Vitis™ Application Acceleration Tutorials

- See 2021.1 Vitis Application Acceleration Development Flow Tutorials -

Vitis HLS Analysis and Optimization

-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
@@ -255,4 +251,4 @@ In summary, the Dataflow viewer enables the following throughput analysis tasks:

Return to Getting Started Pathway — Return to Start of Tutorial

-

Copyright© 2021 Xilinx

+

Copyright© 2021-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks/README.md b/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks/README.md index 2f35901218..785f631573 100644 --- a/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks/README.md +++ b/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks/README.md @@ -1,17 +1,15 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
+ # Using Multiple DDR Banks -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** ## Introduction @@ -50,7 +48,7 @@ The labs in this tutorial use: >**IMPORTANT:** > -> * Before running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/acceleration_installation.html#vhc1571429852245) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). +> * Before running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation-Requirements) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). >* If you run applications on Xilinx® Alveo™ Data Center accelerator cards, ensure the card and software drivers have been correctly installed by following the instructions on the [Alveo Portfolio page](https://www.xilinx.com/products/boards-and-kits/alveo.html). ### Accessing the Tutorial Reference Files @@ -64,7 +62,7 @@ The labs in this tutorial use: ```bash #setup Xilinx Vitis tools, XILINX_VITIS and XILINX_VIVADO will be set in this step. source /settings64.sh. for example: - source /opt/Xilinx/Vitis/2021.1/settings64.sh + source /opt/Xilinx/Vitis/2022.1/settings64.sh #Setup runtime. XILINX_XRT will be set in this step source /opt/xilinx/xrt/setup.sh ``` @@ -79,7 +77,7 @@ The labs in this tutorial use: >**Makefile Options Descriptions** > >* `MODE := hw_emu`: Set the build configuration mode to HW Emulation - >* `PLATFORM := xilinx_u200_gen3x16_xdma_1_202110_1`: Select the target platform + >* `PLATFORM := xilinx_u200_gen3x16_xdma_2_202110_1`: Select the target platform >* `KERNEL_SRC := src/vadd.cpp`: List the kernel source files >* `HOST_SRC := src/host.cpp`: List the host source files @@ -217,4 +215,4 @@ This tutorial showed you how to change the default mapping of ports `in1`, `in2`

Return to Main Page

-

Copyright© 2021 Xilinx

+

Copyright© 2021-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks/reference-files/xrt.ini b/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks/reference-files/xrt.ini index ed5610c8cb..8e5c95ce04 100644 --- a/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks/reference-files/xrt.ini +++ b/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks/reference-files/xrt.ini @@ -1,3 +1,2 @@ [Debug] -opencl_summary=true opencl_trace=true diff --git a/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/README.md b/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/README.md index 9f7d0143b9..b9f58380c8 100644 --- a/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/README.md +++ b/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/README.md @@ -1,17 +1,14 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
# Using Multiple Compute Units -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** ## Introduction @@ -21,7 +18,7 @@ This tutorial demonstrates a flexible kernel linking process to increase the num By default, the Vitis™ core development kit creates one CU for each kernel. A host program can use the same kernel multiple times for different sets of data. In these cases, it is useful to generate multiple CUs of the kernel to let those CUs run concurrently and improve the performance of the overall system. -For more information, see [Creating Multiple Instances of a Kernel](https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vitis+doc;d=buildingdevicebinary.html;a=yzb1524519238289) in the Application Acceleration +For more information, see [Creating Multiple Instances of a Kernel](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Creating-Multiple-Instances-of-a-Kernel) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). During this tutorial, you will: @@ -40,12 +37,12 @@ An OpenCV version of the host code is also provided in the source code directory This tutorial uses: * BASH Linux shell commands -* 2021.2 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_1_202110_1* platform. +* 2022.1 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_2_202110_1* platform. If necessary, it can be easily extended to other versions and platforms. >**IMPORTANT:** > ->* Before to running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/acceleration_installation.html#vhc1571429852245) in the Application Acceleration +>* Before to running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). >* If you run applications on Xilinx® Alveo™ Data Center accelerator cards, ensure the card and software drivers have been correctly installed by following the instructions on the [Alveo Portfolio page](https://www.xilinx.com/products/boards-and-kits/alveo.html). @@ -188,4 +185,4 @@ You have learned how to alter the kernel linking process to execute same kernel

Return to Main Page

-

Copyright© 2021 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/reference-files/solution/xrt.ini b/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/reference-files/solution/xrt.ini index e1523168c2..baa0ff434c 100644 --- a/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/reference-files/solution/xrt.ini +++ b/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/reference-files/solution/xrt.ini @@ -1,3 +1,3 @@ [Debug] -opencl_summary=true opencl_trace=true +device_trace=accel diff --git a/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/reference-files/xrt.ini b/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/reference-files/xrt.ini index a924f3ffec..baa0ff434c 100644 --- a/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/reference-files/xrt.ini +++ b/Hardware_Acceleration/Feature_Tutorials/05-using-multiple-cu/reference-files/xrt.ini @@ -1,3 +1,3 @@ [Debug] opencl_trace=true -data_transfer_trace=accel +device_trace=accel diff --git a/Hardware_Acceleration/Feature_Tutorials/06-controlling-vivado-implementation/README.md b/Hardware_Acceleration/Feature_Tutorials/06-controlling-vivado-implementation/README.md index d432874ecc..753121c59f 100644 --- a/Hardware_Acceleration/Feature_Tutorials/06-controlling-vivado-implementation/README.md +++ b/Hardware_Acceleration/Feature_Tutorials/06-controlling-vivado-implementation/README.md @@ -1,21 +1,18 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
# Controlling Vivado Implementation -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** ## Introduction -The Vitis™ compiler creates kernel objects from the source code, links the kernels with the targeted shell, and runs the assembled design through the Vivado® tool implementation flows. It generates the platform file (`xclbin`) needed to program the FPGA-based acceleration cards. Sometimes, it is essential to use the advanced Vivado synthesis and implementation options to achieve your desired results, including timing closure. The topics discussed here are documented in [Managing Vivado Synthesis and Implementation Results](https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vitis+doc;d=buildingdevicebinary.html;a=hnw1523048617934) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). +The Vitis™ compiler creates kernel objects from the source code, links the kernels with the targeted shell, and runs the assembled design through the Vivado® tool implementation flows. It generates the platform file (`xclbin`) needed to program the FPGA-based acceleration cards. Sometimes, it is essential to use the advanced Vivado synthesis and implementation options to achieve your desired results, including timing closure. The topics discussed here are documented in [Managing Vivado Synthesis and Implementation Results](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Managing-Vivado-Synthesis-and-Implementation-Results) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). ## Tutorial Overview @@ -37,12 +34,12 @@ The Vitis core development kit provides two methods to control the Vivado tool f This tutorial uses: * BASH Linux shell commands -* 2020.2 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_1_202110_1* platform. +* 2022.1 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_2_202110_1* platform. If necessary, it can be easily ported to other versions and platforms. >**IMPORTANT:** > ->* Before running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/acceleration_installation.html#vhc1571429852245) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). +>* Before running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). >* If you run applications on Xilinx® Alveo™ Data Center accelerator cards, ensure the card and software drivers have been correctly installed by following the instructions on the [Alveo Portfolio page](https://www.xilinx.com/products/boards-and-kits/alveo.html). >* Before running this lab, you should be familiar with the [Vitis Getting Started](https://github.com/Xilinx/Vitis-Tutorials/tree/master/Getting_Started/Vitis) tutorial. @@ -73,7 +70,7 @@ The `–-vivado` switch is paired with properties or parameters to configure the * `object_name`: Specifies the object instance to attach to. * `prop_name`: Defines the property_name/value pair which defines both the name and the value to assign. -While you can use `--vivado` options from the `v++` command line, it makes more sense to do some from configuration files specified by the `--config` option. This is explained in [Vitis Compiler Configuration File](https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vitis+doc;d=vitiscommandcompiler.html;a=pni1524163195211) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). In this tutorial, you will use the following options as examples to see how to control Vivado synthesis and implementation: +While you can use `--vivado` options from the `v++` command line, it makes more sense to do some from configuration files specified by the `--config` option. This is explained in [Vitis Compiler Configuration File](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). In this tutorial, you will use the following options as examples to see how to control Vivado synthesis and implementation: * Completely flatten the hierarchy during RTL synthesis by specifying the `FLATTEN_HIERARCHY=full` property. * `--vivado.prop run.my_rm_synth_1.{STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY}={full}` @@ -88,8 +85,8 @@ In this tutorial, the `-–vivado` command options are defined in the `design.cf 1. Compile the kernel with the Vitis compiler and link it with the platform file to produce the device binary (`.xclbin`) using the following commands. ```bash - v++ -t hw --config design.cfg -c -k apply_watermark -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xo ../src/krnl_watermarking.cl - v++ -t hw -s --config design.cfg -R2 -l -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xo + v++ -t hw --config design.cfg -c -k apply_watermark -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xo ../src/krnl_watermarking.cl + v++ -t hw -s --config design.cfg -R2 -l -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xo ``` 2. Open the `design.cfg` file and get familiar with different options. The following list describes some of the command options. @@ -97,7 +94,7 @@ In this tutorial, the `-–vivado` command options are defined in the `design.cf >**Command Options Descriptions** > >* `-t hw`: Build target is hardware - >* `platform=xilinx_u200_gen3x16_xdma_1_202110_1`: Specify the xilinx_u200 platform + >* `platform=xilinx_u200_gen3x16_xdma_2_202110_1`: Specify the xilinx_u200 platform >* `debug=1`: Generate debug info >* `--hls.pre_tcl max_memory.tcl`: Specifies a Tcl script to configure the interface to generate a separate AXI4 interface for each port >* `-c`: Compile the kernel @@ -157,13 +154,13 @@ You can run the Vivado tool in batch mode using a Tcl script or run it interacti Next, reuse the `routed.dcp` checkpoint file generated by the `opt.tcl` script to generate a new platform file (`.xclbin`). To do this, add the `--reuse_impl` option to the `v++` command. This reruns the `--link` process using the already implemented Vivado design checkpoint file (`.dcp`). It runs in much less time than the initial hardware build required. ```bash -v++ -t hw --config design.cfg -l -o 'apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin' apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xo --reuse_impl ./_x/link/vivado/routed.dcp +v++ -t hw --config design.cfg -l -o 'apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin' apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xo --reuse_impl ./_x/link/vivado/routed.dcp ``` From the transcript in the command shell, you can see that the steps to generate the implemented design have been skipped, and the bitstream generation starts. ```bash -INFO: [VPL 60-423] Target device: xilinx_u200_gen3x16_xdma_1_202110_1 +INFO: [VPL 60-423] Target device: xilinx_u200_gen3x16_xdma_2_202110_1 [11:22:58] Run vpl: Step interactive: Started Starting FPGA bitstream generation. ``` @@ -184,8 +181,8 @@ The following section summarizes all the steps to control the Vivado tool implem 2. Generate the platform file (`xclbin`) with `v++` commands. ```bash - v++ -t hw --config design.cfg -c -k apply_watermark -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xo ../src/krnl_watermarking.cl - v++ -t hw -s --config design.cfg -R2 -l -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xo + v++ -t hw --config design.cfg -c -k apply_watermark -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xo ../src/krnl_watermarking.cl + v++ -t hw -s --config design.cfg -R2 -l -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xo ``` 3. Optimize the design with the Vivado tool, and rewrite the routed DCP. @@ -197,7 +194,7 @@ The following section summarizes all the steps to control the Vivado tool implem 4. Reuse the routed DCP to generate the device binary file (`.xclbin`). ```bash - v++ -t hw --config design.cfg -l -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xo --reuse_impl ./_x/link/vivado/routed.dcp + v++ -t hw --config design.cfg -l -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xo --reuse_impl ./_x/link/vivado/routed.dcp ``` 5. This tutorial has provided host code to make it complete to run through various flows. The following commands are references to build the host and run the application. @@ -206,7 +203,7 @@ The following section summarizes all the steps to control the Vivado tool implem #Generate the host executable. g++ -I$XILINX_XRT/include/ -I$XILINX_VIVADO/include/ -Wall -O0 -g -std=c++11 -L$XILINX_XRT/lib/ -lOpenCL -lpthread -lrt -lstdc++ -o 'host' '../src/host.cpp' #Please set correct XCL_EMULATION_MODE manually if running sw_emu and hw_emu modes - ./host apply_watermark.hw.xilinx_u200_gen3x16_xdma_1_202110_1.xclbin ../src/inputImage.bmp ../src/golden.bmp + ./host apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin ../src/inputImage.bmp ../src/golden.bmp ``` ## Conclusion @@ -215,4 +212,4 @@ This tutorial illustrated how to use the `v++` command `--vivado` option to cont

Return to Main Page

-

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/1_overview.md b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/1_overview.md index 88530c7940..2eac8a74af 100755 --- a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/1_overview.md +++ b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/1_overview.md @@ -1,11 +1,8 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
@@ -70,7 +67,7 @@ Start the next step: Migrate the application to

Return to Start of Tutorial

-

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/2_Migrating_to_HBM.md b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/2_Migrating_to_HBM.md index 10427908c7..4c2bef4835 100755 --- a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/2_Migrating_to_HBM.md +++ b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/2_Migrating_to_HBM.md @@ -1,11 +1,8 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
@@ -106,7 +103,7 @@ cd ./../build/DDR_Banks_d512_txSize64 && ./host vadd_hw.xclbin 600 0 1 64; Found Platform Platform Name: Xilinx -DEVICE xilinx_u200_gen3x16_xdma_1_202110_1 +DEVICE xilinx_u200_gen3x16_xdma_2_202110_1 INFO: Reading vadd_hw.xclbin Loading: 'vadd_hw.xclbin' - host loop iteration #0 of 1 total iterations @@ -288,7 +285,7 @@ Start the next step: HBM Bandwidth Results

Return to Start of Tutorial

-

Copyright© 2021 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/3_BW_Explorations.md b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/3_BW_Explorations.md index 5bdb15e45d..86bdebb5ed 100755 --- a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/3_BW_Explorations.md +++ b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/3_BW_Explorations.md @@ -1,11 +1,8 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
@@ -211,4 +208,4 @@ In this tutorial, you learned it's relatively easy to migrate a DDR-based applic

Return to Start of Tutorial

-

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/README.md b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/README.md index 483c220ce0..734cdaef55 100755 --- a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/README.md +++ b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/README.md @@ -1,22 +1,17 @@ - - - - - - +

Vitis™ Application Acceleration Development Flow Tutorials

-
-
+ +

Hardware Acceleration Tutorials

+ See Vitis™ Development Environment on xilinx.com +
# Using HBM -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** ## Introduction - - This tutorial covers essential steps on migrating an existing application using DDR memory to HBM memory. The tutorial begins by explaining the structural differences between DDR and HBM, as well as achievable theoretical bandwidth. The second section uses a simple example with necessary steps to migrate an application from DDR to HBM. ## Before You Begin @@ -26,7 +21,7 @@ This tutorial covers essential steps on migrating an existing application using The labs in this tutorial use: * BASH Linux shell commands. -* 2021.2 Vitis core development kit release and the *xilinx_u200_xdma_201830_2* and *xilinx_u50_gen3x16_xdma_201920_3* platforms. If necessary, it can be easily ported to other versions and platforms. Its also expected that you have a Xilinx® Alveo™ Data Center accelerator card that supports DDR and HBM to run this tutorial. +* 2022.1 Vitis core development kit release and the *xilinx_u200_xdma_201830_2* and *xilinx_u50_gen3x16_xdma_201920_3* platforms. If necessary, it can be easily ported to other versions and platforms. Its also expected that you have a Xilinx® Alveo™ Data Center accelerator card that supports DDR and HBM to run this tutorial. >**IMPORTANT:** > @@ -46,7 +41,7 @@ Development flow of the Vitis Unified Software Platform Documentation (UG1416). 2. Update the `PLATFORM` variable in the `makefile/Makefile` as shown below with the platform intended to be used. ``` ifeq ($(memtype), DDR) - PLATFORM :=xilinx_u200_gen3x16_xdma_1_202110_1 + PLATFORM :=xilinx_u200_gen3x16_xdma_2_202110_1 else PLATFORM :=xilinx_u50_gen3x16_xdma_201920_3 endif @@ -93,7 +88,7 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx
XD018

+

Copyright© 2020–2022 Xilinx
XD018

diff --git a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/makefile/xrt.ini b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/makefile/xrt.ini index 6f0882b09c..dbdf883c48 100644 --- a/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/makefile/xrt.ini +++ b/Hardware_Acceleration/Feature_Tutorials/07-using-hbm/makefile/xrt.ini @@ -1,4 +1,3 @@ [Debug] -opencl_summary=true opencl_trace=true -data_transfer_trace=coarse +device_trace=coarse diff --git a/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem/README.rst b/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem/README.rst index 8146409cbf..3ae16ca0c3 100644 --- a/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem/README.rst +++ b/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem/README.rst @@ -2,7 +2,7 @@ Host Memory Access ======================== -**Version:** Vitis 2021.2 +**Version:** Vitis 2022.1 Some of the recent Xilinx Platforms have an XDMA feature to bypass the DMA operation and allow the kernels to directly access the host memory. The direct host memory access provides an alternate data transfer mechanism compared to XDMA based data transfer and can be useful in some of the scenarios. @@ -18,9 +18,9 @@ XRT and Platform version The following XRT and U250 platform versions are used for this tutorial design. -**XRT Version**: 2021.2 +**XRT Version**: 2022.1 -**Platform**: xilinx_u250_gen3x16_xdma_shell_3_1 +**Platform**: xilinx_u250_gen3x16_xdma_3_1_202020_1 Tutorial Description @@ -280,7 +280,7 @@ Open the vitis_analyzer using the newly generated .run_summary file. .. code:: - vitis_analyzer vadd.hw.run2.xclbin.run_summary + vitis_analyzer xrt.run_summary In the **Kernel and Compute Units** section you can see average CU execution times are now increased compared to the DDR-based run. Now CU takes more time as accessing the remote memory on the host machine is always slower than accessing on-chip memory on the FPGA card. However, increasing CU time is not appearing as an overall negative result as the number of CU executions is increased for each CU. In a host memory-based application, the host CPU is not performing any data transfer operation. This can free up CPU cycles which can then otherwise used to increase the overall application performance. In this example, the free CPU cycles helped in processing more CU execution requests resulting in more accomplished data processing within the same period. @@ -325,4 +325,4 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -Copyright 2020–2021 Xilinx +Copyright 2020–2022 Xilinx diff --git a/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem/reference-files/xrt.ini b/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem/reference-files/xrt.ini index 95af010c98..f172573ef0 100644 --- a/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem/reference-files/xrt.ini +++ b/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem/reference-files/xrt.ini @@ -1,3 +1,2 @@ [Debug] -opencl_summary=true opencl_trace=true diff --git a/Hardware_Acceleration/Feature_Tutorials/README.md b/Hardware_Acceleration/Feature_Tutorials/README.md index e0d3f6c818..45ce4aaea5 100644 --- a/Hardware_Acceleration/Feature_Tutorials/README.md +++ b/Hardware_Acceleration/Feature_Tutorials/README.md @@ -51,4 +51,4 @@ -

Copyright© 2020 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/00-loading-an-alveo-image.md b/Hardware_Acceleration/Introduction/00-loading-an-alveo-image.md index 325b5fb825..92f342a03a 100644 --- a/Hardware_Acceleration/Introduction/00-loading-an-alveo-image.md +++ b/Hardware_Acceleration/Introduction/00-loading-an-alveo-image.md @@ -1,6 +1,6 @@ - @@ -119,4 +119,4 @@ Some things to try to build on this experiment: Read [**Example 1:** Simple Memory Allocation](./01-simple-memory-allocation.md) -

Copyright© 2019-2021 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/01-simple-memory-allocation.md b/Hardware_Acceleration/Introduction/01-simple-memory-allocation.md index 03216b8a05..880f2d6b2c 100644 --- a/Hardware_Acceleration/Introduction/01-simple-memory-allocation.md +++ b/Hardware_Acceleration/Introduction/01-simple-memory-allocation.md @@ -1,6 +1,6 @@

2020.2 Vitis™ - Runtime and System Optimization
Example 0: Loading an Alveo Image

+

Vitis™Hardware Acceleration Introduction Tutorial

See Vitis™ Development Environment on xilinx.com
- @@ -252,4 +252,4 @@ Some things to try to build on this experiment: Read [**Example 2:** Aligned Memory Allocation](./02-aligned-memory-allocation.md) -

Copyright© 2019-2021 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/02-aligned-memory-allocation.md b/Hardware_Acceleration/Introduction/02-aligned-memory-allocation.md index 2d2f96feac..cee445a9dc 100644 --- a/Hardware_Acceleration/Introduction/02-aligned-memory-allocation.md +++ b/Hardware_Acceleration/Introduction/02-aligned-memory-allocation.md @@ -1,6 +1,6 @@

2020.2 Vitis™ - Runtime and System Optimization
Example 1: Simple Memory Allocation

+

Vitis™Hardware Acceleration Introduction Tutorial

See Vitis™ Development Environment on xilinx.com
- @@ -114,4 +114,4 @@ Now we're getting somewhere! Let's try using the OpenCL API to allocate memory Read [**Example 3:** Memory Allocation with XRT](./03-xrt-memory-allocation.md) -

Copyright© 2019-2021 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/03-xrt-memory-allocation.md b/Hardware_Acceleration/Introduction/03-xrt-memory-allocation.md index f167fdda32..709e0b127e 100644 --- a/Hardware_Acceleration/Introduction/03-xrt-memory-allocation.md +++ b/Hardware_Acceleration/Introduction/03-xrt-memory-allocation.md @@ -1,6 +1,6 @@

2020.2 Vitis™ - Runtime and System Optimization
Example 2: Aligned Memory Allocation

+

Vitis™Hardware Acceleration Introduction Tutorial

See Vitis™ Development Environment on xilinx.com
- @@ -207,4 +207,4 @@ Some things to try to build on this experiment: Read [**Example 4:** Parallelizing the Data Path](./04-parallelizing-the-data-path.md) -

Copyright© 2019-2021 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/04-parallelizing-the-data-path.md b/Hardware_Acceleration/Introduction/04-parallelizing-the-data-path.md index 771a1c6f38..29c7bc7e51 100644 --- a/Hardware_Acceleration/Introduction/04-parallelizing-the-data-path.md +++ b/Hardware_Acceleration/Introduction/04-parallelizing-the-data-path.md @@ -1,6 +1,6 @@

2020.2 Vitis™ - Runtime and System Optimization - Acceleration Basics

+

Vitis™Hardware Acceleration Introduction Tutorial

See Vitis™ Development Environment on xilinx.com
- @@ -217,4 +217,4 @@ those transfer times. Read [**Example 5:** Optimizing Compute and Transfer](./05-optimizing-compute-and-transfer.md) -

Copyright© 2019-2021 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/05-optimizing-compute-and-transfer.md b/Hardware_Acceleration/Introduction/05-optimizing-compute-and-transfer.md index 1cb3a014c0..5cc8119a30 100644 --- a/Hardware_Acceleration/Introduction/05-optimizing-compute-and-transfer.md +++ b/Hardware_Acceleration/Introduction/05-optimizing-compute-and-transfer.md @@ -1,6 +1,6 @@

2020.2 Vitis™ - Runtime and System Optimization
Example 4: Parallelizing the Data Path

+

Vitis™Hardware Acceleration Introduction Tutorial

See Vitis™ Development Environment on xilinx.com
- @@ -250,4 +250,4 @@ Some things to try to build on this experiment: Read [**Example 6:** Meet the Other Shoe](./06-meet-the-other-shoe.md) -

Copyright© 2019-2021 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/06-meet-the-other-shoe.md b/Hardware_Acceleration/Introduction/06-meet-the-other-shoe.md index 7f92035cc7..72e46f4f3d 100644 --- a/Hardware_Acceleration/Introduction/06-meet-the-other-shoe.md +++ b/Hardware_Acceleration/Introduction/06-meet-the-other-shoe.md @@ -1,6 +1,6 @@

2020.2 Vitis™ - Runtime and System Optimization
Example 5: Optimizing Compute and Transfer

+

Vitis™Hardware Acceleration Introduction Tutorial

See Vitis™ Development Environment on xilinx.com
- @@ -93,4 +93,4 @@ But despair not! Now it’s time to look at something real. Read [**Example 7:** Image Resizing with Vitis Vision](./07-image-resizing-with-vitis-vision.md) -

Copyright© 2019-2021 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/07-image-resizing-with-vitis-vision.md b/Hardware_Acceleration/Introduction/07-image-resizing-with-vitis-vision.md index 48512f854f..d3bf412ce1 100644 --- a/Hardware_Acceleration/Introduction/07-image-resizing-with-vitis-vision.md +++ b/Hardware_Acceleration/Introduction/07-image-resizing-with-vitis-vision.md @@ -1,6 +1,6 @@

2020.2 Vitis™ - Runtime and System Optimization - Acceleration Basics

+

Vitis™Hardware Acceleration Introduction Tutorial

See Vitis™ Development Environment on xilinx.com
- @@ -169,4 +169,4 @@ We mentioned briefly earlier that doing additional processing in the FPGA fabric Read [**Example 8:** Pipelining Operations with Vitis Vision](./08-vitis-vision-pipeline.md) -

Copyright© 2019-2021 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/08-vitis-vision-pipeline.md b/Hardware_Acceleration/Introduction/08-vitis-vision-pipeline.md index 24ee9e9ff5..5ddaa59651 100644 --- a/Hardware_Acceleration/Introduction/08-vitis-vision-pipeline.md +++ b/Hardware_Acceleration/Introduction/08-vitis-vision-pipeline.md @@ -1,6 +1,6 @@

2020.2 Vitis™ - Runtime and System Optimization
Example 7: Image Resizing with Vitis Vision

+

Vitis™Hardware Acceleration Introduction Tutorial

See Vitis™ Development Environment on xilinx.com
- @@ -156,4 +156,4 @@ That concludes our runtime introductory tutorial! We certainly hope you found it take the opportunity to smash that like button and subscr... wait, wrong venue. But do take the time to review our [many other tutorials](../README.md), and thanks for reading! -

Copyright© 2019-2021 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/README.md b/Hardware_Acceleration/Introduction/README.md index 088035bbac..bde529f558 100644 --- a/Hardware_Acceleration/Introduction/README.md +++ b/Hardware_Acceleration/Introduction/README.md @@ -9,7 +9,7 @@ ## Introduction -***Version: Vitis 2021.2*** +***Version: Vitis 2022.1*** Xilinx FPGAs and Versal ACAP devices are uniquely suitable for low-latency acceleration of high performance algorithms and workloads. With the demise of traditional Moore's Law scaling, design-specific architectures(DSAs) are becoming the tool of choice for developers needing the optimal balance of capability, power, latency, and flexibility. But, approaching FPGA and ACAP development from a purely software background can seem daunting. @@ -59,4 +59,4 @@ so if this is your first time here we recommend proceeding through the tutorial + Or: How I learned to love FPGAs -

Copyright© 2020 Xilinx

+

Copyright© 2019-2022 Xilinx

diff --git a/Hardware_Acceleration/Introduction/design_source/xrt.ini b/Hardware_Acceleration/Introduction/design_source/xrt.ini index 5f859837aa..6709828ccf 100644 --- a/Hardware_Acceleration/Introduction/design_source/xrt.ini +++ b/Hardware_Acceleration/Introduction/design_source/xrt.ini @@ -1,5 +1,4 @@ # Start of debug group [Debug] -profile = true -timeline_trace = true -data_transfer_trace = coarse +opencl_trace = true +device_trace = coarse diff --git a/Hardware_Acceleration/README.md b/Hardware_Acceleration/README.md index 7b6df77738..21d3f153ee 100644 --- a/Hardware_Acceleration/README.md +++ b/Hardware_Acceleration/README.md @@ -110,4 +110,4 @@ The methodology for developing optimized accelerated applications is comprised o

2020.2 Vitis™ - Runtime and System Optimization
Example 8: Image Processing Pipeline with Vitis Vision

+

Vitis™Hardware Acceleration Introduction Tutorial

See Vitis™ Development Environment on xilinx.com
-

Copyright© 2020-2021 Xilinx

+

Copyright© 2020-2022 Xilinx

diff --git a/Jenkinsfile b/Jenkinsfile index df00137b84..16f33c813b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -7,4 +7,4 @@ VitisLibPipeline (branch: 'master', libname: 'Vitis-Tutorials', TARGETS: 'hls_cs disable_standardization: "true", allowed_modes:"sw_emu,hw_emu,hw", yml:'2022.1/tutorial.yml', tql:'2022.1/tutorial.tql', - email: 'alokgupt@amd.com', TOOLVERSION: '2022.1_daily_latest') + email: 'randyh@xilinx.com', select_case: '/group/xcoswmktg/randyh/sprite-test-list.txt', TOOLVERSION: '2022.1_daily_latest')