diff --git a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/README.md b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/README.md index bf20fc7b8d..070a4050bf 100644 --- a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/README.md +++ b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/README.md @@ -49,8 +49,8 @@ This tutorial is based on matrix multiplication which is a usual algorithm in Ma To follow this tutorial you need to understand the architecture of the *AI Engine-ML* as well as the art of buffer descriptor programming: -- **AI Engine ML Architecture:**: [am020](https://docs.xilinx.com/r/en-US/am020-versal-aie-ml) -- **Programming Buffer Descriptors with Tiling parameters:** [UG1603](https://docs.xilinx.com/r/en-US/ug1603-ai-engine-ml-kernel-coding) +- **AI Engine ML Architecture:**: [am020](https://docs.amd.com/r/en-US/am020-versal-aie-ml) +- **Programming Buffer Descriptors with Tiling parameters:** [UG1603](https://docs.amd.com/r/en-US/ug1603-ai-engine-ml-kernel-coding) A short introduction to **AI Engine-ML** architecture is available [here](AIEngineMLArchitecture.md). diff --git a/AI_Engine_Development/AIE-ML/Design_Tutorials/03-AIE-ML-lenet_tutorial/README.md b/AI_Engine_Development/AIE-ML/Design_Tutorials/03-AIE-ML-lenet_tutorial/README.md index 4e0716dab1..477c5531e0 100755 --- a/AI_Engine_Development/AIE-ML/Design_Tutorials/03-AIE-ML-lenet_tutorial/README.md +++ b/AI_Engine_Development/AIE-ML/Design_Tutorials/03-AIE-ML-lenet_tutorial/README.md @@ -98,11 +98,11 @@ Note: This tutorial targets the VEK280 Production board (see https://www.xilinx. ### *Documentation*: Explore AI Engine-ML Architecture -* [AM020 AI Engine-ML Architecture Manual](https://docs.xilinx.com/r/en-US/am020-versal-aie-ml) +* [AM020 AI Engine-ML Architecture Manual](https://docs.amd.com/r/en-US/am020-versal-aie-ml) -* [Versal AI Edge Introduction](https://docs.xilinx.com/v/u/en-US/wp518-ai-edge-intro) +* [Versal AI Edge Introduction](https://docs.amd.com/v/u/en-US/wp518-ai-edge-intro) -* [Tiling Parameters and Buffer Descriptors](https://docs.xilinx.com/r/en-US/ug1603-ai-engine-ml-kernel-graph/Tiling-Parameters-and-Buffer-Descriptors) +* [Tiling Parameters and Buffer Descriptors](https://docs.amd.com/r/en-US/ug1603-ai-engine-ml-kernel-graph/Tiling-Parameters-and-Buffer-Descriptors) @@ -114,17 +114,17 @@ Note: This tutorial targets the VEK280 Production board (see https://www.xilinx. Tools Documentation: -* [AI Engine Documentation](https://docs.xilinx.com/search/all?filters=Document_ID~%2522UG1603%2522_%2522UG1079%2522&content-lang=en-US) +* [AI Engine Documentation](https://docs.amd.com/search/all?filters=Document_ID~%2522UG1603%2522_%2522UG1079%2522&content-lang=en-US) To build and run the LeNet tutorial,the following tools should be downloaded/installed: -* Install the [Vitis Software Platform 2024.1](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) +* Install the [Vitis Software Platform 2024.1](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) * Obtain a license to enable Beta Devices in AMD tools (to use the `xilinx_vek280_es1_base_202410_1` platform) * Obtain licenses for AI Engine-ML tools -* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT) +* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT) * Download and set up the [VEK280 Vitis Platform for 2024.1](https://www.xilinx.com/support/download/index.html) @@ -560,8 +560,8 @@ cd ../../; | --- | --- | |--target \| -t [hw\|hw_emu]|Specifies the build target.| |--package \| -p|Packages the final product at the end of the Vitis compile and link build process.| -|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| -|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| +|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| +|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| |--package.boot_mode \|Where \ specifies Boot mode used for running the application in emulation or on hardware.| |--package.image_format|Where \ specifies \ output image file format. `ext4`: Linux file system and `fat32`: Windows file system.| |--package.sd_file|Where \ specifies an ELF or other data file to package into the `sd_card` directory/image. This option can be used repeatedly to specify multiple files to add to the `sd_card`.| @@ -782,7 +782,7 @@ The software design in the LeNet tutorial consists of the following sections: ### AI Engine-ML Kernels and Graph Representation -An AI Engine-ML kernel is a C/C++ program written using specialized intrinsic calls that targets the VLIW vector processor. The AI Engine-ML compiler compiles the kernel code to produce an executable ELF file for each of the AI Engine-MLs being used in the design. Review the [AI Engine-ML Kernel Programming](https://docs.xilinx.com/r/en-US/ug1603-ai-engine-ml-kernel-graph/Single-Kernel-Programming) section in the AI Engine-ML Documentation for a high-level overview of kernel programming. These kernels can be stitched together to function as AI Engine-ML graphs written in C++. +An AI Engine-ML kernel is a C/C++ program written using specialized intrinsic calls that targets the VLIW vector processor. The AI Engine-ML compiler compiles the kernel code to produce an executable ELF file for each of the AI Engine-MLs being used in the design. Review the [AI Engine-ML Kernel Programming](https://docs.amd.com/r/en-US/ug1603-ai-engine-ml-kernel-graph/Single-Kernel-Programming) section in the AI Engine-ML Documentation for a high-level overview of kernel programming. These kernels can be stitched together to function as AI Engine-ML graphs written in C++. The AI Engine-ML compiler writes a summary of compilation results called `lenet.aiecompile_summary`. You can view the graph by running the following command: @@ -809,7 +809,7 @@ The Array view offers a comprehensive perspective, illustrating the AI Engine, A ### Data Flow Graph -This section describes the overall data-flow graph specification of the LeNet design that is compiled by the AI Engine-ML compiler. Refer to [AI Engine-ML Graph Programming](https://docs.xilinx.com/r/en-US/ug1603-ai-engine-ml-kernel-graph/Introduction-to-Graph-Programming) section in the AI Engine-ML Documentation for information on ADF graphs. +This section describes the overall data-flow graph specification of the LeNet design that is compiled by the AI Engine-ML compiler. Refer to [AI Engine-ML Graph Programming](https://docs.amd.com/r/en-US/ug1603-ai-engine-ml-kernel-graph/Introduction-to-Graph-Programming) section in the AI Engine-ML Documentation for information on ADF graphs. The overall graph definition of the design is contained in the `graph.cpp` file. The following steps describe the definition of the graph. @@ -906,7 +906,7 @@ read_access(tensor01.out[0])=tiling({ .buffer_dimension = { 2, 4 ,144},.tiling_d }); ``` -The write access pattern for the memory tile on the input side as well as the read access pattern on the output side, both follow a 3D linear addressing scheme. These addressing scheme are specifically configured within the graph, ensuring efficient data handling through a defined tiling parameter. Review [Tiling-Parameters-Specification](https://docs.xilinx.com/r/en-US/ug1603-ai-engine-ml-kernel-graph/Tiling-Parameters-Specification) to understand the tiling parameter for different addressing modes. +The write access pattern for the memory tile on the input side as well as the read access pattern on the output side, both follow a 3D linear addressing scheme. These addressing scheme are specifically configured within the graph, ensuring efficient data handling through a defined tiling parameter. Review [Tiling-Parameters-Specification](https://docs.amd.com/r/en-US/ug1603-ai-engine-ml-kernel-graph/Tiling-Parameters-Specification) to understand the tiling parameter for different addressing modes. #### LeNet Top Level Application Define a top level application file (`graph.cpp` in this design) @@ -945,7 +945,7 @@ The `dma_hls` kernel is an IP, which contains `dma_mm2s` and `dma_s2mm`. `dma_mm ### PS Host Application -The LeNet tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine-ML graph and data mover PL kernels. Review [Programming the PS Host Application Section in the AI Engine-ML Documentation](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) to understand the process to create a host application. +The LeNet tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine-ML graph and data mover PL kernels. Review [Programming the PS Host Application Section in the AI Engine-ML Documentation](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) to understand the process to create a host application. In addition to the PS host application (`main.cpp`), the AI Engine-ML control code must also be compiled. This control code (`aie_control_xrt.cpp`) is generated by the AI Engine-ML compiler when compiling the AI Engine-ML design graph and kernel code. The AI Engine-ML control code is used by the PS host application to do the following: @@ -1084,7 +1084,7 @@ vcdanalyze --vcd x$(VCD_FILE_NAME).vcd --xpe ``` -2. If you do not already have it installed, download and install [PDM for Versal Version 2024.1](https://www.xilinx.com/products/design-tools/power-design-manager.html). For full documentation of PDM, see [this page](https://docs.xilinx.com/r/en-US/ug1556-power-design-manager). +2. If you do not already have it installed, download and install [PDM for Versal Version 2024.1](https://www.xilinx.com/products/design-tools/power-design-manager.html). For full documentation of PDM, see [this page](https://docs.amd.com/r/en-US/ug1556-power-design-manager). 3. Create the project and choose the default part as XCVE2802-VSVH1760-2MP-E-S. @@ -1107,7 +1107,7 @@ Due to profiling issues, a script method was employed to calculate vector load a The following documents provide supplemental information for this tutorial. -#### [AI Engine-ML Documentation](https://docs.xilinx.com/r/en-US/ug1603-ai-engine-ml-kernel-graph) +#### [AI Engine-ML Documentation](https://docs.amd.com/r/en-US/ug1603-ai-engine-ml-kernel-graph) Contains sections on how to develop AI Engine-ML graphs, how to use the AI Engine-ML compiler, AI Engine-ML simulation, and performance analysis. @@ -1121,15 +1121,15 @@ The following are the links to the XRT information used by this tutorial: * [XRT AIE API](https://github.com/Xilinx/XRT/blob/master/src/runtime_src/core/include/experimental/xrt_aie.h): Documents the AI Engine-ML XRT API calls. -#### [Vitis Unified Software Development Platform Documentation](https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation) +#### [Vitis Unified Software Development Platform Documentation](https://docs.amd.com/v/u/en-US/ug1416-vitis-documentation) The following are the links to Vitis related information referenced in this tutorial: -* [Vitis Application Acceleration Development Flow Documentation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration) +* [Vitis Application Acceleration Development Flow Documentation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration) * [Vitis Application Acceleration Development Flow Tutorials](https://github.com/Xilinx/Vitis-Tutorials) -* [Vitis HLS](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls) +* [Vitis HLS](https://docs.amd.com/r/en-US/ug1399-vitis-hls)

Copyright © 2020–2024 Advanced Micro Devices, Inc

diff --git a/AI_Engine_Development/AIE-ML/Feature_Tutorials/05-AI-engine-versal-integration/README.md b/AI_Engine_Development/AIE-ML/Feature_Tutorials/05-AI-engine-versal-integration/README.md index c7ec5eb6e5..08a023ad5b 100644 --- a/AI_Engine_Development/AIE-ML/Feature_Tutorials/05-AI-engine-versal-integration/README.md +++ b/AI_Engine_Development/AIE-ML/Feature_Tutorials/05-AI-engine-versal-integration/README.md @@ -238,7 +238,7 @@ For `ai_engine_0` the names are provided in the `graph.h`. For the design, as an has the name **DataIn1** which is the interface name. -You can see the `v++` switches in more detail in the [Vitis Unified Software Platform Documentation]([https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command)). +You can see the `v++` switches in more detail in the [Vitis Unified Software Platform Documentation]([https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command)). To build the design run the follow command: @@ -431,7 +431,7 @@ The **Summary** View displays the compilation runtime, the version of the compil After the graph has been compiled, you can simulate your design with the `aiesimulator` command. This uses a cycle-approximate model to test your graph and get preliminary throughput information early in the design cycle, while the PL developers continue to work on the platform for the application. -**Note**: Simulating the design with VCD will increase simulation runtime. To learn more about this feature, see [AI Engine SystemC Simulator](https://docs.xilinx.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1076-ai-engine-environment). +**Note**: Simulating the design with VCD will increase simulation runtime. To learn more about this feature, see [AI Engine SystemC Simulator](https://docs.amd.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1076-ai-engine-environment). 1. To run simulation use the command: @@ -771,7 +771,7 @@ In this tutorial you learned the following: * How to execute the design for hardware emulation. * How to execute the design on the board. -To read more about the use of Vitis in the AI Engine flow see: [UG1076: AI Engine Tools and Flows User Guide: Integrating the Application Using the Vitis Tool Flow](https://docs.xilinx.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1076-ai-engine-environment). +To read more about the use of Vitis in the AI Engine flow see: [UG1076: AI Engine Tools and Flows User Guide: Integrating the Application Using the Vitis Tool Flow](https://docs.amd.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1076-ai-engine-environment). #### Support diff --git a/AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/README.md b/AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/README.md index 363a5a45b5..730a74d624 100644 --- a/AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/README.md +++ b/AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/README.md @@ -1,4 +1,4 @@ - +

AIE-ML Development

See AMD Vitis™ Development Environment on xilinx.com
 @@ -84,7 +84,7 @@ Look at [Normalization Version 1 Graph Code](./normalization_v1/aie/graph.h): repetition_count(k_norm)=ROW*COL/K_ROW/K_COL; ``` -* The write access and read access of the memtile is linear. For tiling parameters usage, you may refer to [Tiling Parameters Specification](https://docs.xilinx.com/r/en-US/ug1603-ai-engine-ml-kernel-coding/Tiling-Parameters-Specification). +* The write access and read access of the memtile is linear. For tiling parameters usage, you may refer to [Tiling Parameters Specification](https://docs.amd.com/r/en-US/ug1603-ai-engine-ml-kernel-coding/Tiling-Parameters-Specification). ``` mtxA = shared_buffer::create({COL,ROW}, 1, 1); @@ -147,7 +147,7 @@ However, the design will hang. Hang detection is supported via multiple design f make aiesim ``` - And Refer to [Lock Stall Analysis](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Lock-Stall-Analysis) for steps to analyze the root cause of the hang. The stalls of the kernels are highlighted as: + And Refer to [Lock Stall Analysis](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Lock-Stall-Analysis) for steps to analyze the root cause of the hang. The stalls of the kernels are highlighted as: ![AIE Stalls in SIM](./images/aie_stalls1.PNG) @@ -157,7 +157,7 @@ However, the design will hang. Hang detection is supported via multiple design f make package TARGET=hw ``` - And refer to [AIE status report](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Analyzing-AI-Engine-Status-in-Hardware) for steps to analyze the root cause of the hang. The status in hardware is like: + And refer to [AIE status report](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Analyzing-AI-Engine-Status-in-Hardware) for steps to analyze the root cause of the hang. The status in hardware is like: ![AIE Status in HW](./images/aie_status1.PNG) @@ -221,7 +221,7 @@ So, the graph throughput via simulation can be computed as: The kernel execution time can be profiled by multiple ways, for example: -1. By utilizing the tile counter in the kernel code: [Profiling Kernel Code](https://docs.xilinx.com/r/en-US/ug1603-ai-engine-ml-kernel-coding/Profiling-Kernel-Code) +1. By utilizing the tile counter in the kernel code: [Profiling Kernel Code](https://docs.amd.com/r/en-US/ug1603-ai-engine-ml-kernel-coding/Profiling-Kernel-Code) 2. Use `--profile` option of AIE simulation to get the function time: ![Version 2 Kernel Profile](./images/kernel_profile2.PNG) diff --git a/AI_Engine_Development/AIE/AIE.rst b/AI_Engine_Development/AIE/AIE.rst index 43110fefba..d3617fd402 100644 --- a/AI_Engine_Development/AIE/AIE.rst +++ b/AI_Engine_Development/AIE/AIE.rst @@ -1,4 +1,4 @@ -####################################### +####################################### AI Engine Development ####################################### @@ -26,13 +26,13 @@ Getting Started AI Engine Documentation ============================================================= -To easily find the right documentation corresponding to the development stage you are at, we recommend you use the `AI Engine Design Process Hub `_. +To easily find the right documentation corresponding to the development stage you are at, we recommend you use the `AI Engine Design Process Hub `_. The major documentation for AI Engine includes: -* *Versal ACAP AI Engine Architecture Manual* (`AM009 `_) -* *AI Engine Tools and Flows* (`UG1076 `_) -* *AI Engine Kernel and Graph Programming Guide* (`UG1079 `_) +* *Versal ACAP AI Engine Architecture Manual* (`AM009 `_) +* *AI Engine Tools and Flows* (`UG1076 `_) +* *AI Engine Kernel and Graph Programming Guide* (`UG1079 `_) AI Engine Training @@ -53,7 +53,7 @@ Environment Settings .. important:: - Before beginning a tutorial, read and follow the `Vitis Software Platform Release Notes `_ (v2023.2) for setting up software and installing the VCK190 base platform. + Before beginning a tutorial, read and follow the `Vitis Software Platform Release Notes `_ (v2023.2) for setting up software and installing the VCK190 base platform. Run the following steps to set up the environment (do **NOT** apply to tutorials that do not use the VCK190 base platform): diff --git a/AI_Engine_Development/AIE/Design_Tutorials/01-aie_lenet_tutorial/README.md b/AI_Engine_Development/AIE/Design_Tutorials/01-aie_lenet_tutorial/README.md index 232913dee9..8923c84be8 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/01-aie_lenet_tutorial/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/01-aie_lenet_tutorial/README.md @@ -97,7 +97,7 @@ Note: This tutorial targets the VCK190 Production board (see https://www.xilinx. ### *Documentation*: Explore AI Engine Architecture -* [AM009 AI Engine Architecture Manual](https://docs.xilinx.com/r/en-US/am009-versal-ai-engine/Revision-History) +* [AM009 AI Engine Architecture Manual](https://docs.amd.com/r/en-US/am009-versal-ai-engine/Revision-History) * [Versal ACAP AI Engines for Dummies](https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-ACAP-AI-Engines-for-Dummies/ba-p/1132493) @@ -111,17 +111,17 @@ Note: This tutorial targets the VCK190 Production board (see https://www.xilinx. Tools Documentation: -* [AI Engine Documentation](https://docs.xilinx.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) +* [AI Engine Documentation](https://docs.amd.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) To build and run the LeNet tutorial, you will need the following tools downloaded/installed: -* Install the [Vitis Software Platform 2024.1](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) +* Install the [Vitis Software Platform 2024.1](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) * Obtain a license to enable Beta Devices in AMD tools (to use the `xilinx_vck190_base_202410_1` platform) * Obtain licenses for AI Engine tools -* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT) +* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT) * Download and set up the [VCK190 Vitis Platform for 2024.1](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html) @@ -557,8 +557,8 @@ cd ../../; | --- | --- | |--target \| -t [hw\|hw_emu]|Specifies the build target.| |--package \| -p|Packages the final product at the end of the Vitis compile and link build process.| -|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| -|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| +|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| +|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| |--package.boot_mode \|Where \ specifies Boot mode used for running the application in emulation or on hardware.| |--package.image_format|Where \ specifies \ output image file format. `ext4`: Linux file system and `fat32`: Windows file system.| |--package.sd_file|Where \ specifies an ELF or other data file to package into the `sd_card` directory/image. This option can be used repeatedly to specify multiple files to add to the `sd_card`.| @@ -776,7 +776,7 @@ The software design in the LeNet tutorial consists of the following sections: ### AI Engine Kernels and Graph Representation -An AI Engine kernel is a C/C++ program written using specialized intrinsic calls that targets the VLIW vector processor. The AI Engine compiler compiles the kernel code to produce an executable ELF file for each of the AI Engines being used in the design. Review the [AI Engine Kernel Programming](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding/Single-Kernel-Programming) section in the AI Engine Documentation for a high-level overview of kernel programming. These kernels can be stitched together to function as AI Engine graphs written in C++. +An AI Engine kernel is a C/C++ program written using specialized intrinsic calls that targets the VLIW vector processor. The AI Engine compiler compiles the kernel code to produce an executable ELF file for each of the AI Engines being used in the design. Review the [AI Engine Kernel Programming](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding/Single-Kernel-Programming) section in the AI Engine Documentation for a high-level overview of kernel programming. These kernels can be stitched together to function as AI Engine graphs written in C++. The AI Engine compiler writes a summary of compilation results called `lenet.aiecompile_summary`. You can view the graph by running the following command: @@ -795,7 +795,7 @@ Note: Also defined in the AI Engine graph are the weights (`corelut.h`). The ### Data Flow Graph -This section describes the overall data-flow graph specification of the LeNet design which is compiled by the AI Engine compiler. Refer to [AI Engine Graph Programming](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding/Introduction-to-Graph-Programming) section in the AI Engine Documentation for information on ADF graphs. +This section describes the overall data-flow graph specification of the LeNet design which is compiled by the AI Engine compiler. Refer to [AI Engine Graph Programming](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding/Introduction-to-Graph-Programming) section in the AI Engine Documentation for information on ADF graphs. The overall graph definition of the design is contained in the `graph.cpp` file. The following steps describe the definition of the graph. @@ -897,7 +897,7 @@ The `dma_hls` kernel is an IP which contains `dma_mm2s` and `dma_s2mm`. `dma_mm2 ### PS Host Application -The LeNet tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine graph and data mover PL kernels. Review [Programming the PS Host Application Section in the AI Engine Documentation](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) to understand the process to create a host application. +The LeNet tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine graph and data mover PL kernels. Review [Programming the PS Host Application Section in the AI Engine Documentation](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) to understand the process to create a host application. In addition to the PS host application (`main.cpp`), the AI Engine control code must also be compiled. This control code (`aie_control_xrt.cpp`) is generated by the AI Engine compiler when compiling the AI Engine design graph and kernel code. The AI Engine control code is used by the PS host application to do the following: @@ -1058,7 +1058,7 @@ cd $(BUILD_TARGET_DIR); \ vcdanalyze --vcd x$(VCD_FILE_NAME).vcd --xpe ``` -2. If you do not already have it installed, download and install [XPE for Versal Version 2024.1](https://www.xilinx.com/products/technology/power/xpe.html). For full documentation of XPE, see [this page](https://docs.xilinx.com/r/en-US/ug1275-xilinx-power-estimator-versal). +2. If you do not already have it installed, download and install [XPE for Versal Version 2024.1](https://www.xilinx.com/products/technology/power/xpe.html). For full documentation of XPE, see [this page](https://docs.amd.com/r/en-US/ug1275-xilinx-power-estimator-versal). 3. Load the `graph.xpe` into XPE to see the AI Engine power comsumption and resource utilization for lenet design: @@ -1074,7 +1074,7 @@ A summary of resource utilization and power is given in the following table. The following documents provide supplemental information for this tutorial. -#### [AI Engine Documentation](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding/Overview) +#### [AI Engine Documentation](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding/Overview) Contains sections on how to develop AI Engine graphs, how to use the AI Engine compiler, AI Engine simulation, and performance analysis. @@ -1088,15 +1088,15 @@ The following are links to the XRT information used by this tutorial: * [XRT AIE API](https://github.com/Xilinx/XRT/blob/master/src/runtime_src/core/include/experimental/xrt_aie.h): Documents the AI Engine XRT API calls. -#### [Vitis Unified Software Development Platform Documentation](https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation) +#### [Vitis Unified Software Development Platform Documentation](https://docs.amd.com/v/u/en-US/ug1416-vitis-documentation) The following are links to Vitis related information referenced in this tutorial: -* [Vitis Application Acceleration Development Flow Documentation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration) +* [Vitis Application Acceleration Development Flow Documentation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration) * [Vitis Application Acceleration Development Flow Tutorials](https://github.com/Xilinx/Vitis-Tutorials) -* [Vitis HLS](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls) +* [Vitis HLS](https://docs.amd.com/r/en-US/ug1399-vitis-hls) ##### Revision History diff --git a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/README.md b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/README.md index 9d417b3d6e..e1473efe09 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/README.md @@ -379,23 +379,23 @@ Finally, software platform is generated with the `platform generate` command. Th ## References -* [Creating Embedded Platforms in Vitis](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Creating-Embedded-Platforms-in-Vitis) +* [Creating Embedded Platforms in Vitis](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Creating-Embedded-Platforms-in-Vitis) * [Vitis Tutorials](https://github.com/Xilinx/Vitis-Tutorials) * [Vitis Tutorials: Platform Creation](https://github.com/Xilinx/Vitis-Tutorials/tree/master/Vitis_Platform_Creation) * [Versal Custom Platform Creation Tutorial](https://github.com/Xilinx/Vitis-Tutorials/blob/master/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md) -* [Vivado Design Suite Tcl Command Reference](https://docs.xilinx.com/access/sources/dita/map?url=ug835-vivado-tcl-commands&ft:locale=en-US +* [Vivado Design Suite Tcl Command Reference](https://docs.amd.com/access/sources/dita/map?url=ug835-vivado-tcl-commands&ft:locale=en-US ) -* [Software Command-Line Tool (XSCT)](https://docs.xilinx.com/r/en-US/ug1400-vitis-embedded/Software-Command-Line-Tool) -* [AI Engine Documentation](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Overview) -* [AI Engine Product Guide](https://docs.xilinx.com/access/sources/dita/map?url=pg358-versal-ai-engine&ft:locale=en-US) +* [Software Command-Line Tool (XSCT)](https://docs.amd.com/r/en-US/ug1400-vitis-embedded/Software-Command-Line-Tool) +* [AI Engine Documentation](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Overview) +* [AI Engine Product Guide](https://docs.amd.com/access/sources/dita/map?url=pg358-versal-ai-engine&ft:locale=en-US) * [AXI Debug Hub IP](https://www.xilinx.com/products/intellectual-property/axi_dbg_hub.html#overview) * [Simulation Clock and Reset Generator IP](https://www.xilinx.com/products/intellectual-property/sim-rst-gen.html) * [AXI SmartConnect IP](https://www.xilinx.com/products/intellectual-property/smartconnect.html) * [AXI Verification IP](https://www.xilinx.com/products/intellectual-property/axi-vip.html) * [Clocking Wizard IP](https://www.xilinx.com/products/intellectual-property/clocking_wizard.html) * [Processor Reset System Module IP](https://www.xilinx.com/products/intellectual-property/proc_sys_reset.html) -* [CIPS Product Guide](https://docs.xilinx.com/access/sources/dita/map?url=pg352-cips&ft:locale=en-US) -* [Versal ACAP Programmable Network on Chip and Integrated Memory Controller Product Guide](https://docs.xilinx.com/access/sources/dita/map?url=pg313-network-on-chip&ft:locale=en-US) +* [CIPS Product Guide](https://docs.amd.com/access/sources/dita/map?url=pg352-cips&ft:locale=en-US) +* [Versal ACAP Programmable Network on Chip and Integrated Memory Controller Product Guide](https://docs.amd.com/access/sources/dita/map?url=pg313-network-on-chip&ft:locale=en-US) ### Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_02_AI_Engine_Design/README.md b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_02_AI_Engine_Design/README.md index 621c48b270..2b97f1e66b 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_02_AI_Engine_Design/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_02_AI_Engine_Design/README.md @@ -194,16 +194,16 @@ ULBF Output0: Throughput 6.65915e+08 Samples/s, i.e. 2.66366e+09 Bytes/s ## References -* [AI Engine Documentation](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Overview) -* [AI Engine Documentation: AI Engine Programming](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment) (to learn more about AI Engine graph and kernels) -* [AI Engine Kernel and Graph Programming Guide](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding/Intrinsics) (lists of all the intrinsic APIs and data types supported in the current release) -* [AI Engine Documentation: Run Time Graph Control API](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding/Run-Time-Graph-Control-API) -* [AI Engine Kernel and Graph Programming Guide](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding/Graph-Programming-Model) -* [AI Engine Documentation: Adaptive Data Flow Graph Specification](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding/Adaptive-Data-Flow-Graph-Specification-Reference) +* [AI Engine Documentation](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Overview) +* [AI Engine Documentation: AI Engine Programming](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment) (to learn more about AI Engine graph and kernels) +* [AI Engine Kernel and Graph Programming Guide](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding/Intrinsics) (lists of all the intrinsic APIs and data types supported in the current release) +* [AI Engine Documentation: Run Time Graph Control API](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding/Run-Time-Graph-Control-API) +* [AI Engine Kernel and Graph Programming Guide](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding/Graph-Programming-Model) +* [AI Engine Documentation: Adaptive Data Flow Graph Specification](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding/Adaptive-Data-Flow-Graph-Specification-Reference) * [XAPP1352 Beamforming Implementation on AI Engine](https://www.xilinx.com/search/support-keyword-search.html#q=xapp1352) -* [AI Engine System C Simulator](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/AI-Engine-SystemC-Simulator) -* [AI Engine Profiling Graph Throughput](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Profiling-Graph-Throughput) -* [Vivado Design Suite User Guide: Implementation](https://docs.xilinx.com/r/en-US/ug904-vivado-implementation/Implementing-the-Design) +* [AI Engine System C Simulator](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/AI-Engine-SystemC-Simulator) +* [AI Engine Profiling Graph Throughput](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Profiling-Graph-Throughput) +* [Vivado Design Suite User Guide: Implementation](https://docs.amd.com/r/en-US/ug904-vivado-implementation/Implementing-the-Design) ### Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_03_PL_Design/README.md b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_03_PL_Design/README.md index a9b3fce2ba..a798ce0c21 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_03_PL_Design/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_03_PL_Design/README.md @@ -278,7 +278,7 @@ Each uplink AI Engine graph has eight input data ports, 32 input coefficient por Remember, our system instantiates three uplink graphs, so the total number of ULBF PL kernels becomes: three ``ulbf_data``, 12 ``ulbf_coeffs``, and 12 ``ulbf_slaves``. ### References -* [Vitis Application Acceleration Development Flow Documentation, Developing Applications, RTL Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration) - This is a reference on how to create your own custom RTL kernels. Please note that the PL kernels in this design do not completely adhere to the recommended guidelines. +* [Vitis Application Acceleration Development Flow Documentation, Developing Applications, RTL Kernels](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration) - This is a reference on how to create your own custom RTL kernels. Please note that the PL kernels in this design do not completely adhere to the recommended guidelines. #### Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_04_AI_Engine_and_PL_Integration/README.md b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_04_AI_Engine_and_PL_Integration/README.md index cf83fe616f..8c50bd9e5e 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_04_AI_Engine_and_PL_Integration/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_04_AI_Engine_and_PL_Integration/README.md @@ -298,12 +298,12 @@ If you built from scratch, you can open the block design in the Vivado project t ## References -* [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Linking the System](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow) -* [Vitis Application Acceleration Development Flow Documentation: Building and Running the Application, Building the Device Binary, Linking the Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-System) -* [Vitis Compiler Command](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) -* [Vitis Compiler Configuration File](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) -* [Vitis Application Acceleration Development Flow Documentation: Building and Running the Application, Build Targets](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Building-and-Running-the-Application) - HW vs HW_EMU -* [Vivado Design Suite User Guide: Implementation](https://docs.xilinx.com/r/en-US/ug904-vivado-implementation/Implementing-the-Design) +* [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Linking the System](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow) +* [Vitis Application Acceleration Development Flow Documentation: Building and Running the Application, Building the Device Binary, Linking the Kernels](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-System) +* [Vitis Compiler Command](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +* [Vitis Compiler Configuration File](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) +* [Vitis Application Acceleration Development Flow Documentation: Building and Running the Application, Build Targets](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Building-and-Running-the-Application) - HW vs HW_EMU +* [Vivado Design Suite User Guide: Implementation](https://docs.amd.com/r/en-US/ug904-vivado-implementation/Implementing-the-Design) ### Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_05_Baremetal_Host_Application/README.md b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_05_Baremetal_Host_Application/README.md index e1608fbfde..4ee987103a 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_05_Baremetal_Host_Application/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_05_Baremetal_Host_Application/README.md @@ -42,7 +42,7 @@ generate-platform.sh -name vck190_baremetal \ -domain psv_cortexa72_0:standalone \ -out-dir build ``` -The options are explained in the [AI Engine Documentation: Building a Bare-Metal System](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Building-a-Bare-Metal-System). +The options are explained in the [AI Engine Documentation: Building a Bare-Metal System](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Building-a-Bare-Metal-System). ### Compiling the PS Application Source Code @@ -225,7 +225,7 @@ The main function then calls the `test_ulbf` function. It starts the ULBF kernel ## References * [Xilinx Standalone Library Documentation OS and Libraries Document Collection](https://www.xilinx.com/search/support-keyword-search.html#q=ug643) -* [AI Engine Documentation: Building a Bare-Metal System](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Building-a-Bare-Metal-System) +* [AI Engine Documentation: Building a Bare-Metal System](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Building-a-Bare-Metal-System) ### Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md index b11ee18bb7..2d01683237 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md @@ -11,7 +11,7 @@ After the AI Engine graph is compiled and linked with the PL kernels, the PS application is compiled, and all the required outputs are generated, the next step in the build process is to package the required files to configure and boot the AMD Versal™ device. This requires the use of the AMD Vitis™ compiler ``--package`` command. For Versal adaptive SOCs, the programmable device image (PDI) file is used to boot and program the hardware device. -In this module, you will package the bare-metal system to generate the final bootable image (PDI) for running hardware emulation and for running it on the VCK190 board. Refer to [AI Engine Documentation: Packaging](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Packaging) for more details on this packaging process. +In this module, you will package the bare-metal system to generate the final bootable image (PDI) for running hardware emulation and for running it on the VCK190 board. Refer to [AI Engine Documentation: Packaging](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Packaging) for more details on this packaging process. ## Building the Design: Hardware Emulation @@ -144,10 +144,10 @@ NB: HW_emu  run will take long hours to run which makes software collapse , hw ## References -* [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Packaging](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Packaging) -* [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Running the System](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow) -* [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Deploying the System](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Deploying-the-System) -* [Vitis Compiler Command Options](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-General-Options) +* [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Packaging](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Packaging) +* [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Running the System](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow) +* [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Deploying the System](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Deploying-the-System) +* [Vitis Compiler Command Options](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-General-Options) ### Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md index 584e1e0b91..730eaa2b5e 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md @@ -229,7 +229,7 @@ This script uses the XSA from Module 04 and the custom Petalinux image to genera * [PetaLinux Tools Documentation](https://www.xilinx.com/search/support-keyword-search.html#q=ug1144) * [Bootgen User Guide](https://www.xilinx.com/search/support-keyword-search.html#q=ug1283) * [Libmetal and OpenAMP](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2022_2/ug1186-zynq-openamp-gsg.pdf) -* [Versal Platform Creation Tutorial](https://docs.xilinx.com/r/en-US/Vitis-Tutorials-Vitis-Platform-Creation/Custom-Platform-Creation-Tutorial-on-Versal) +* [Versal Platform Creation Tutorial](https://docs.amd.com/r/en-US/Vitis-Tutorials-Vitis-Platform-Creation/Custom-Platform-Creation-Tutorial-on-Versal) ### Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_08_Linux_SW_Application/README.md b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_08_Linux_SW_Application/README.md index ab0810e739..7f647d31ab 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_08_Linux_SW_Application/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_08_Linux_SW_Application/README.md @@ -23,7 +23,7 @@ The individual commands are explained later on in this module. A top-level PS application running on the Cortex-A72 processor controls the AI Engine graph and the PL kernels. In Module 05, you created a PS host application for a bare-metal system. In this module, you will create a PS host application that runs on a Linux operating system (built in Module 07). -Detailed descriptions of compiler flags, include directories, and linker flags are available in [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Compile the Embedded Application for the Cortex-A72 Processor](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow). +Detailed descriptions of compiler flags, include directories, and linker flags are available in [AI Engine Documentation: Integrating the Application Using the Vitis Tools Flow, Compile the Embedded Application for the Cortex-A72 Processor](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow). Linux host applications use the Xilinx Runtime (XRT) API to control the PL and AI Engine kernels. In this tutorial, XRT is used to access the AI Engine graph and generic UIO drivers to access the PL kernels. @@ -75,7 +75,7 @@ else if(reset_done == 0) { log_plnx << "[Beamformer] AIE reset done successfully" << std::endl; } ``` -If the `xrtResetAIEArray` function fails, the AI Engine reset has not been accomplished successfully and a system reboot might be required. See the [API Documentation](https://docs.xilinx.com/r/en-US/Vitis-Tutorials-AI-Engine-Development/Load-AIE-XCLBIN). +If the `xrtResetAIEArray` function fails, the AI Engine reset has not been accomplished successfully and a system reboot might be required. See the [API Documentation](https://docs.amd.com/r/en-US/Vitis-Tutorials-AI-Engine-Development/Load-AIE-XCLBIN). This function does not orchestrate system reset but _only_ resets the AI Engine array. @@ -83,7 +83,7 @@ This function does not orchestrate system reset but _only_ resets the AI Engine The host application loads the AI Engine with the XCLBIN with the ``xclloadxclbin()`` function. -The following snippet of code shows usage in the application shows how to load AIE. See the [API Documentation](https://docs.xilinx.com/r/en-US/Vitis-Tutorials-AI-Engine-Development/Load-AIE-XCLBIN). +The following snippet of code shows usage in the application shows how to load AIE. See the [API Documentation](https://docs.amd.com/r/en-US/Vitis-Tutorials-AI-Engine-Development/Load-AIE-XCLBIN). ```C++ //In load_xclbin() diff --git a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/README.md b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/README.md index 0b4c998200..1a958b4889 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/README.md @@ -48,28 +48,28 @@ This tutorial targets the [VCK190 ES board](https://www.xilinx.com/products/boar ### *Documentation*: Explore AI Engine Architecture -* [AM009 AI Engine Architecture Manual](https://docs.xilinx.com/r/en-US/am009-versal-ai-engine/Revision-History) +* [AM009 AI Engine Architecture Manual](https://docs.amd.com/r/en-US/am009-versal-ai-engine/Revision-History) * [Versal ACAP AI Engines for Dummies](https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-ACAP-AI-Engines-for-Dummies/ba-p/1132493) * [AI Engine Tools lounge](https://www.xilinx.com/member/versal_ai_tools_ea.html) -* [AI Engine Documentation](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Overview) +* [AI Engine Documentation](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Overview) ### *Tools*: Installing the Tools 1. Obtain a license to enable beta devices in AMD tools (to use the VCK190 platform). 2. Obtain licenses for AI Engine tools. -3. Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT). +3. Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT). 4. Download and set up the [VCK190 Vitis Platform for 2024.1](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html). -5. Follow the instructions to install PetaLinux tools in the PetaLinux Tools Documentation ([UG1144](https://docs.xilinx.com/r/en-US/ug1144-petalinux-tools-reference-guide)). +5. Follow the instructions to install PetaLinux tools in the PetaLinux Tools Documentation ([UG1144](https://docs.amd.com/r/en-US/ug1144-petalinux-tools-reference-guide)). 6. Download the [VCK190 PetaLinux 2024.1 BSP](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html) from the Versal AI Core Series VCK190 HeadStart Early Access Site. To build and run the Beamforming tutorial, download and install the following tools: -* [Vitis™ Unified Software Development Platform 2024.1](https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation) -* [The Xilinx RunTime (XRT)](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) +* [Vitis™ Unified Software Development Platform 2024.1](https://docs.amd.com/v/u/en-US/ug1416-vitis-documentation) +* [The Xilinx RunTime (XRT)](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) * [PetaLinux Tools](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html) ### *Environment*: Setting Up Your Shell Environment diff --git a/AI_Engine_Development/AIE/Design_Tutorials/04-Polyphase-Channelizer/README.md b/AI_Engine_Development/AIE/Design_Tutorials/04-Polyphase-Channelizer/README.md index 4d13dda765..bacc7b9668 100644 --- a/AI_Engine_Development/AIE/Design_Tutorials/04-Polyphase-Channelizer/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/04-Polyphase-Channelizer/README.md @@ -1,4 +1,4 @@ - +

AI Engine Development

@@ -210,7 +210,7 @@ The build process will generate the SD card image in the ```04-Polyphase-Channel ## Estimating Power Using the Power Design Manager -The Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities to the largest Versal and AMD Kria™ SOM products. It is the preferred power estimation tool for the Versal product family. More information can be found on the [Power Design Manager (PDM)](https://www.xilinx.com/products/design-tools/power-design-manager.html) product page and in the Power Design Manager User Guide [(UG1556)](https://docs.xilinx.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1556-power-design-manager). +The Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities to the largest Versal and AMD Kria™ SOM products. It is the preferred power estimation tool for the Versal product family. More information can be found on the [Power Design Manager (PDM)](https://www.xilinx.com/products/design-tools/power-design-manager.html) product page and in the Power Design Manager User Guide [(UG1556)](https://docs.amd.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1556-power-design-manager). The PDM has three modes to estimate power: @@ -218,7 +218,7 @@ The PDM has three modes to estimate power: * **Import Compilation Flow**: The file generated from XPE or Vivado Report Power is imported into the PDM after compiling the design. * **Import Simulation Flow**: The file generated from XPE or Vivado Report Power is imported into the PDM after simulating the design. -This example uses the **Import Compilation Flow** mode to perform a Vectorless Power Analysis as defined in the Vivado Design Suite User Guide: Power Analysis and Optimization [(UG907)](https://docs.xilinx.com/r/en-US/ug907-vivado-power-analysis-optimization/Vectorless-Power-Analysis). This estimate is refined by running a simulation of the AI Engine portion of the design and updating the initial estimate. +This example uses the **Import Compilation Flow** mode to perform a Vectorless Power Analysis as defined in the Vivado Design Suite User Guide: Power Analysis and Optimization [(UG907)](https://docs.amd.com/r/en-US/ug907-vivado-power-analysis-optimization/Vectorless-Power-Analysis). This estimate is refined by running a simulation of the AI Engine portion of the design and updating the initial estimate. ### Step 1: Building the Design for VCK190 and Executing Power Targets diff --git a/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/AIE/README.md b/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/AIE/README.md index 998a338928..e6daf969f7 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/AIE/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/AIE/README.md @@ -1,4 +1,4 @@ - +

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 @@ -28,7 +28,7 @@ ### Design Build -In this section, you build and run the 2D-FFT design using the AI Engine implementation. You compile and integrate the AI Engine design into a larger system design (including the PL kernels and PS host application). Review the [Integrating the Application section in the AI Engine Documentation](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow) for the general flow. +In this section, you build and run the 2D-FFT design using the AI Engine implementation. You compile and integrate the AI Engine design into a larger system design (including the PL kernels and PS host application). Review the [Integrating the Application section in the AI Engine Documentation](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow) for the general flow. At the end of this section, the design flow generates a new directory (called `build/`). Underneath are sub-directories named `(cint16_dsns-cfloat_dsns)/fft2d_$(MAT_ROWS)x$(MAT_COLS)/x$(FFT_2D_INSTS)/` (for example, `cint16_dsns/fft2d_1024x2048/x1/`) depending on the datatype `${FFT_2D_DT}`, value of matrix dimensions `${MAT_ROWS}`, `${MAT_COLS}` and the number of instances `$(FFT_2D_INSTS)` chosen in the build. Each sub-directory contains the `hw_emu/` and/or `hw/` subfolders. The respective subfolders contain `Work/` and `libadf.a`, outputs from the AI Engine compiler, the host app executable, and the builds, targeted to `hw` or `hw_emu`, respectively. The `hw_emu/` subfolder contains the build for the hardware emulation. The `hw/` subfolder contains the build for hardware running on a VCK190 board. @@ -136,7 +136,7 @@ v++ --target hw_emu --hls.clock 312500000:dma_hls --platform xilinx_vck190_base_ $(DESIGN_REPO)/pl_src/dma_hls.cpp -o $(BUILD_TARGET_DIR)/dma_hls.hw_emu.xo ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) for a detailed description of all Vitis compiler switches. The following table provides a summary of the switches used. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) for a detailed description of all Vitis compiler switches. The following table provides a summary of the switches used. |Switch|Description| | --- | --- | @@ -194,7 +194,7 @@ aiecompiler -include=$(AIE_SRC_REPO) -include=/L1/include/aie \ ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment) for full AI Engine programming environment documentation. +See [this page](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment) for full AI Engine programming environment documentation. The following table provides a summary of the switches used. @@ -259,7 +259,7 @@ If `EN_TRACE` is enabled, the following Vitis compiler flags are also set: ``` For higher values of `FFT_2D_INSTS`, only the `strmInp_from_colwiseFFT` port is profiled to avoid too much data. -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Device-Binary) for a detailed description of Vitis linking options. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Device-Binary) for a detailed description of Vitis linking options. |Switch|Description| | --- | --- | @@ -269,8 +269,8 @@ See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceler |--verbose|Display verbose/debug information.| |--config |Specifies a configuration file containing V++ switches.| |--output \| -o|Specifies the name of the output file generated by the V++ command. In this design the outputs of the DMA HLS kernels and the PL kernels interfacing with the AI Engine are in XO files.| -|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| -|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| +|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| +|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| The information to tell the linker how to connect the AI Engine and PL kernels together is described in a configuration file, `system_configs/x$(FFT_2D_INSTS).cfg`. The file describes the overall connection scheme of the system. @@ -292,7 +292,7 @@ param=hw_emu.enableProfiling=false ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) for a detailed description of the Vitis compiler configuration file. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) for a detailed description of the Vitis compiler configuration file. |Switch|Comment| @@ -348,7 +348,7 @@ aarch64-xilinx-linux-g++ -mcpu=cortex-a72.cortex-a53 -march=armv8-a+crc -fstack- -ladf_api_xrt -lxrt_coreutil -o $(BUILD_TARGET_DIR)/fft_2d_aie_xrt.elf ``` -See [this page](https://xilinx.github.io/XRT/master/html/index.html) for XRT documentation. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Best-Practices-for-Host-Programming) for details of host application programming. +See [this page](https://xilinx.github.io/XRT/master/html/index.html) for XRT documentation. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Best-Practices-for-Host-Programming) for details of host application programming. |Switch|Description| @@ -418,14 +418,14 @@ If `XRT_ROOT` is set, the following Vitis compiler flags are also set: --package.sd_dir $(XRT_ROOT) ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Packaging) for more details about packaging the system. +See [this page](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Packaging) for more details about packaging the system. |Switch|Description| | --- | --- | |--target \| -t [hw\|hw_emu]|Specifies the build target.| |--package \| -p|Packages the final product at the end of the Vitis compile and link build process.| -|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| -|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| +|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| +|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| |--package.boot_mode \|Where \ specifies . Boot mode used for running the application in emulation or on hardware.| |--package.image_format|Where \ specifies the \ output image file format. `ext4` is the Linux file system and `fat32` is the Windows file system.| |--package.sd_file|Where \ specifies an ELF or other data file to package into the `sd_card` directory/image. This option can be used repeatedly to specify multiple files to add to the `sd_card` directory.| @@ -765,7 +765,7 @@ AI Engine kernels are configured for `cint16 / 4bytes`, and the streaming interf ### AI Engine Kernels and Graph Representation -An AI Engine kernel is a C/C++ program written using specialized intrinsic calls that target the VLIW vector processor. The AI Engine compiler compiles the kernel code to produce an executable ELF file for each AI Engines used in the design. These kernels can be stitched together as AI Engine graphs written in C++. In this design, the AI Engine compiler summarizes compilation results. Review the [AI Engine Kernel Programming](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding) section in the AI Engine documentation for a high-level overview of kernel programming. You can view the graph by running the following command: +An AI Engine kernel is a C/C++ program written using specialized intrinsic calls that target the VLIW vector processor. The AI Engine compiler compiles the kernel code to produce an executable ELF file for each AI Engines used in the design. These kernels can be stitched together as AI Engine graphs written in C++. In this design, the AI Engine compiler summarizes compilation results. Review the [AI Engine Kernel Programming](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding) section in the AI Engine documentation for a high-level overview of kernel programming. You can view the graph by running the following command: `vitis_analyzer $(BUILD_TARGET_DIR)/Work/graph.aiecompile_summary` @@ -787,7 +787,7 @@ The overall graph definition of the design is contained in the `graph.cpp` file. #### Defining the Graph Class -Define the graph classes using objects defined in the appropriate name space. It must include the ADF library and [Vitis DSP Library](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/index.html) for FFIT. A general specification is put in for the ADF namespace: +Define the graph classes using objects defined in the appropriate name space. It must include the ADF library and [Vitis DSP Library](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/index.html) for FFIT. A general specification is put in for the ADF namespace: ``` // FFTrows_graph FFT point size... @@ -998,14 +998,14 @@ int dma_hls( } ``` -The `dma_hls` kernel also specifies HLS pragmas to help optimize the kernel code and adhere to interface protocols. See [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas) for detailed documentation of all HLS pragmas. A summary of the HLS pragmas used in the kernel is provided in the following table: +The `dma_hls` kernel also specifies HLS pragmas to help optimize the kernel code and adhere to interface protocols. See [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas) for detailed documentation of all HLS pragmas. A summary of the HLS pragmas used in the kernel is provided in the following table: |Switch|Description| | --- | --- | -|#pragma HLS INTERFACE|In C/C++ code, all input and output operations are performed, in zero time, through formal function arguments. In an RTL design, these same input and output operations must be performed through a port in the design interface and typically operate using a specific input/output (I/O) protocol. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-interface).| -|#pragma HLS PIPELINE II=1|Reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the config_compile -pipeline_style command, but can be overridden in the PIPELINE pragma or directive. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline).| -|#pragma HLS dataflow|The DATAFLOW pragma enables task-level pipelining, allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and the overall throughput of the design. See [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow) for more information.| -|#pragma HLS loop_tripcount|When manually applied to a loop, it specifies the total number of iterations a loop performs. The `LOOP_TRIPCOUNT` pragma or directive is for analysis only and does not impact the synthesis results. See [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-loop_tripcount) for more information.| +|#pragma HLS INTERFACE|In C/C++ code, all input and output operations are performed, in zero time, through formal function arguments. In an RTL design, these same input and output operations must be performed through a port in the design interface and typically operate using a specific input/output (I/O) protocol. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-interface).| +|#pragma HLS PIPELINE II=1|Reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the config_compile -pipeline_style command, but can be overridden in the PIPELINE pragma or directive. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline).| +|#pragma HLS dataflow|The DATAFLOW pragma enables task-level pipelining, allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and the overall throughput of the design. See [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow) for more information.| +|#pragma HLS loop_tripcount|When manually applied to a loop, it specifies the total number of iterations a loop performs. The `LOOP_TRIPCOUNT` pragma or directive is for analysis only and does not impact the synthesis results. See [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-loop_tripcount) for more information.| @@ -1014,7 +1014,7 @@ The `dma_hls` kernel also specifies HLS pragmas to help optimize the kernel code ### PS Host Application -The 2D-FFT AI Engine tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine graph and data mover PL kernels. Review the [Programming the PS Host Application](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) section in the AI Engine documentation to understand the process of creating a host application. +The 2D-FFT AI Engine tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine graph and data mover PL kernels. Review the [Programming the PS Host Application](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) section in the AI Engine documentation to understand the process of creating a host application. In addition to the PS host application (`fft_2d_aie_app.cpp`), the AI Engine control code must also be compiled. The AI Engine compiler generates this control code (`aie_control_xrt.cpp`) when compiling the AI Engine design graph and kernel code. The PS host application uses the AI Engine control code for the following purposes: @@ -1248,7 +1248,7 @@ Throughput is measured in mega-samples transferred per second (MSPS). It is meas trace_buffer_size=500M ``` - For more information, refer to the [xrt.ini](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/xrt.ini-File) documentation. + For more information, refer to the [xrt.ini](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/xrt.ini-File) documentation. 2. After execution on the board, transfer the generated `device_trace_0.csv`, `hal_host_trace.csv`, and `xrt.run_summary` files back to your system. diff --git a/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/HLS/README.md b/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/HLS/README.md index 2f033c1de5..d88d74312d 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/HLS/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/HLS/README.md @@ -1,4 +1,4 @@ - +

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 @@ -148,13 +148,13 @@ v++ --target hw_emu --hls.clock 250000000:dma_hls --platform xilinx_vck190_base_ $(DESIGN_REPO)/pl_src/dma_hls.cpp -o $(BUILD_TARGET_DIR)/dma_hls.hw_emu.xo ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) for a detailed description of all Vitis compiler switches. The following table provides a summary of the switches used. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) for a detailed description of all Vitis compiler switches. The following table provides a summary of the switches used. |Switch|Description| | --- | --- | |--target \| -t [hw\|hw_emu]|Specifies the build target.| -|--hls.pre_tcl \|Specifies a Tcl file containing Tcl commands for `vitis_hls` to source before running `csynth_design`. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/hls-Options) for details about HLS options.| +|--hls.pre_tcl \|Specifies a Tcl file containing Tcl commands for `vitis_hls` to source before running `csynth_design`. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/hls-Options) for details about HLS options.| |--platform \| -f|Specifies the name of a supported acceleration platform as specified by the $PLATFORM_REPO_PATHS environment variable or the full path to the platform XPFM file.| |--save-temps \| -s|Directs the Vitis compiler command to save intermediate files/directories created during the compilation and link process. Use the `--temp_dir` option to specify a location to write the intermediate files.| |--temp_dir |This allows you to manage the location where the tool writes temporary files created during the build process. The Vitis compiler writes the temporary results and removes them unless the `--save-temps` option is also specified.| @@ -236,7 +236,7 @@ If `EN_TRACE` is enabled, the following Vitis compiler flags are also set: ``` For higher values of `FFT_2D_INSTS`, only the `strmInp_from_colwiseFFT` port is profiled to avoid too much data. -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-System) for a detailed description of Vitis linking options. The following table provides a summary of the switches used. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-System) for a detailed description of Vitis linking options. The following table provides a summary of the switches used. |Switch|Description| | --- | --- | @@ -245,9 +245,9 @@ See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceler |--temp_dir |This allows you to manage the location where the tool writes temporary files created during the build process. The temporary results are written by the Vitis compiler, and then removed, unless the `--save-temps` option is also specified.| |--verbose|Display verbose/debug information.| |--output \| -o|Specifies the name of the output file generated by the V++ command. In this design the outputs of the HLS/DSP kernels with their interfacing with the PL kernels are in XO files.| -|--vivado.prop \|Specifies properties for the AMD Vivado™ Design Suite to be used during synthesis and implementation of the FPGA binary (xsa). See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/vivado-Options) for detailed Vivado options.| -|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| -|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| +|--vivado.prop \|Specifies properties for the AMD Vivado™ Design Suite to be used during synthesis and implementation of the FPGA binary (xsa). See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/vivado-Options) for detailed Vivado options.| +|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| +|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| |--config |Specifies a configuration file containing V++ switches.| The information to tell the linker how to connect the HLS/DSP and PL kernels together is described in a configuration file, `system_configs/x$(FFT_2D_INSTS).cfg`. The file describes the overall connection scheme of the system. @@ -271,7 +271,7 @@ param=hw_emu.enableProfiling=false param=compiler.addOutputTypes=hw_export ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) for a detailed description of the Vitis compiler configuration file. A summary of the configuration options used is provided in the following table. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) for a detailed description of the Vitis compiler configuration file. A summary of the configuration options used is provided in the following table. |Switch|Comment| @@ -316,7 +316,7 @@ aarch64-xilinx-linux-g++ -mcpu=cortex-a72.cortex-a53 -march=armv8-a+crc -fstack ``` -See [this page](https://xilinx.github.io/XRT/2023.2/html/index.html) for XRT documentation. See [this page]((https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Best-Practices-for-Host-Programming) for details of host application programming. +See [this page](https://xilinx.github.io/XRT/2023.2/html/index.html) for XRT documentation. See [this page]((https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Best-Practices-for-Host-Programming) for details of host application programming. |Switch|Description| @@ -382,15 +382,15 @@ If the `XRT_ROOT` is set, the following Vitis compiler flags are also set: --package.sd_dir $(XRT_ROOT) ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Packaging) for more details about packaging the system. +See [this page](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Packaging) for more details about packaging the system. |Switch|Description| | --- | --- | |--target \| -t [hw\|hw_emu]|Specifies the build target.| |--package \| -p|Packages the final product at the end of the Vitis compile and link build process.| -|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| -|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| +|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| +|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) for more information.| |--package.boot_mode \|Where \ specifies Boot mode used for running the application in emulation or on hardware.| |--package.image_format|Where \ specifies \ output image file format. `ext4` is the Linux file system and `fat32` is the Windows file system.| |--package.sd_file|Where \ specifies an ELF or other data file to package into the `sd_card` directory/image. This option can be used repeatedly to specify multiple files to add to the `sd_card`.| @@ -625,9 +625,9 @@ ITER_LOOP_FFT_COLS:for(int i = 0; i < iterCnt; ++i) { ##### Subfunctions are Pipelined and Set Up in DATAFLOW -Pipelining reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the `config_compile -pipeline_style` command but can be overridden in the [PIPELINE pragma](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline) or directive. +Pipelining reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the `config_compile -pipeline_style` command but can be overridden in the [PIPELINE pragma](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline) or directive. -The [DATAFLOW pragma](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow) enables task-level pipelining as described in [Control Driven Task Level Parallelism: Dataflow Optimization](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Control-driven-Task-level-Parallelism), allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and the overall throughput of the design. +The [DATAFLOW pragma](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow) enables task-level pipelining as described in [Control Driven Task Level Parallelism: Dataflow Optimization](https://docs.amd.com/r/en-US/ug1399-vitis-hls/Control-driven-Task-level-Parallelism), allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and the overall throughput of the design. All operations are performed sequentially in a C description. Without directives that limit resources (such as pragma HLS allocation), the Vitis HLS tool seeks to minimize latency and improve concurrency. However, data dependencies can limit this. For example, functions or loops that access arrays must finish all read/write accesses to the arrays before they are complete. This prevents the next function or loop that consumes the data from starting the operation. The DATAFLOW optimization enables the operations in a function or loop to start operation before the previous function or loop completes all its operations. @@ -723,7 +723,7 @@ For timing closure of the whole design, different implementation properties are For the purposes of achieving timing closure for the 256 x 512 point x10 and 1024 x 2048 point x10 designs, over 200 implementation strategies were used, out of which three met timing. Out of that, those with the least power were chosen as the implementation strategy in the `v++ -l / make xsa` step. -For more information about implementation strategies, see the _Vivado Implementation User Guide_ [UG904](https://docs.xilinx.com/r/en-US/ug904-vivado-implementation) +For more information about implementation strategies, see the _Vivado Implementation User Guide_ [UG904](https://docs.amd.com/r/en-US/ug904-vivado-implementation) @@ -732,7 +732,7 @@ For more information about implementation strategies, see the _Vivado Implementa ### HLS/DSP Kernel Representation -An HLS/DSP kernel comprises the [Fast Fourier Transform LogiCORE IP](https://www.xilinx.com/products/intellectual-property/fft.html#overview) instantiated in the HLS kernel using the [HLS FFT library](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/FFT-IP-Library). Additionally, the kernel has the input and output wrappers for reading and writing data into and out of the FFT core. You can view the function call graph in the Vitis HLS GUI, as shown in the following figure. +An HLS/DSP kernel comprises the [Fast Fourier Transform LogiCORE IP](https://www.xilinx.com/products/intellectual-property/fft.html#overview) instantiated in the HLS kernel using the [HLS FFT library](https://docs.amd.com/r/en-US/ug1399-vitis-hls/FFT-IP-Library). Additionally, the kernel has the input and output wrappers for reading and writing data into and out of the FFT core. You can view the function call graph in the Vitis HLS GUI, as shown in the following figure. ![Image of 2D-FFT HLS Function Call Graph](images/fft_2d_hls_function_call_graph.PNG) @@ -743,7 +743,7 @@ An HLS/DSP kernel comprises the [Fast Fourier Transform LogiCORE IP](https://www ### Data Flow -This section describes the overall data flow of the 2D-FFT design using the HLS FFT library, which is compiled using the Vitis compiler. Refer to [C/C++ Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Developing-PL-Kernels-using-C) for information. +This section describes the overall data flow of the 2D-FFT design using the HLS FFT library, which is compiled using the Vitis compiler. Refer to [C/C++ Kernels](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Developing-PL-Kernels-using-C) for information. The overall definition of the FFT-2D kernel is defined in `$(PL_SRC_REPO)/fft_2d.cpp`. @@ -1108,14 +1108,14 @@ void writeOut_row(hls::stream> &strm_out, } ``` -The `fft_2d` kernel specifies HLS pragmas to help optimize the kernel code and adhere to interface protocols. See [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas) for detailed documentation of all HLS pragmas. A summary of the HLS pragmas used in this kernel is given in the following table. +The `fft_2d` kernel specifies HLS pragmas to help optimize the kernel code and adhere to interface protocols. See [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas) for detailed documentation of all HLS pragmas. A summary of the HLS pragmas used in this kernel is given in the following table. |Switch|Description| | --- | --- | -|#pragma HLS INTERFACE|In C/C++ code, all input and output operations are performed, in zero time, through formal function arguments. In a RTL design, these same input and output operations must be performed through a port in the design interface and typically operate using a specific input/output (I/O) protocol. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-interface).| -|#pragma HLS PIPELINE II=1|Reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the `config_compile -pipeline_style` command, but can be overridden in the `PIPELINE` pragma or directive. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline).| -|#pragma HLS dataflow|The `DATAFLOW` pragma enables task-level pipelining, allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and increasing the overall throughput of the design. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow).| -|#pragma HLS array_reshape|The `ARRAY_RESHAPE` pragma reforms the array with vertical remapping and concatenating elements of arrays by increasing bit widths. This reduces the amount of block RAM consumed while providing parallel access to the data. This pragma creates a new array with fewer elements but with greater bit width, allowing more data to be accessed in a single clock cycle. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-array_reshape).| +|#pragma HLS INTERFACE|In C/C++ code, all input and output operations are performed, in zero time, through formal function arguments. In a RTL design, these same input and output operations must be performed through a port in the design interface and typically operate using a specific input/output (I/O) protocol. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-interface).| +|#pragma HLS PIPELINE II=1|Reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the `config_compile -pipeline_style` command, but can be overridden in the `PIPELINE` pragma or directive. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline).| +|#pragma HLS dataflow|The `DATAFLOW` pragma enables task-level pipelining, allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and increasing the overall throughput of the design. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow).| +|#pragma HLS array_reshape|The `ARRAY_RESHAPE` pragma reforms the array with vertical remapping and concatenating elements of arrays by increasing bit widths. This reduces the amount of block RAM consumed while providing parallel access to the data. This pragma creates a new array with fewer elements but with greater bit width, allowing more data to be accessed in a single clock cycle. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-array_reshape).| @@ -1207,14 +1207,14 @@ int dma_hls( } ``` -The `dma_hls` kernel also specifies HLS pragmas to help optimize the kernel code and adhere to interface protocols. See [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas) for detailed documentation of all HLS pragmas. A summary of the HLS pragmas used in this kernel is given in the following table. +The `dma_hls` kernel also specifies HLS pragmas to help optimize the kernel code and adhere to interface protocols. See [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas) for detailed documentation of all HLS pragmas. A summary of the HLS pragmas used in this kernel is given in the following table. |Switch|Description| | --- | --- | -|#pragma HLS INTERFACE|In C/C++ code, all input and output operations are performed, in zero time, through formal function arguments. In a RTL design, these same input and output operations must be performed through a port in the design interface and typically operate using a specific input/output (I/O) protocol. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-interface).| -|#pragma HLS PIPELINE II=1|Reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the `config_compile -pipeline_style` command, but can be overridden in the `PIPELINE` pragma or directive. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline).| -|#pragma HLS dataflow|The `DATAFLOW` pragma enables task-level pipelining, allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and increasing the overall throughput of the design. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow).| -|#pragma HLS loop_tripcount|When manually applied to a loop, this pragma specifies the total number of iterations performed by a loop. The `LOOP_TRIPCOUNT` pragma or directive is for analysis only, and does not impact the results of synthesis. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-loop_tripcount).| +|#pragma HLS INTERFACE|In C/C++ code, all input and output operations are performed, in zero time, through formal function arguments. In a RTL design, these same input and output operations must be performed through a port in the design interface and typically operate using a specific input/output (I/O) protocol. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-interface).| +|#pragma HLS PIPELINE II=1|Reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the `config_compile -pipeline_style` command, but can be overridden in the `PIPELINE` pragma or directive. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline).| +|#pragma HLS dataflow|The `DATAFLOW` pragma enables task-level pipelining, allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and increasing the overall throughput of the design. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow).| +|#pragma HLS loop_tripcount|When manually applied to a loop, this pragma specifies the total number of iterations performed by a loop. The `LOOP_TRIPCOUNT` pragma or directive is for analysis only, and does not impact the results of synthesis. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-loop_tripcount).| @@ -1223,7 +1223,7 @@ The `dma_hls` kernel also specifies HLS pragmas to help optimize the kernel code ### PS Host Application -The 2D-FFT HLS/DSP tutorial uses the embedded processing system (PS) as an external controller to control the 2D-FFT and data mover PL kernels. Review the [Programming the PS Host Application](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) section in the documentation to understand the process to create a host application. +The 2D-FFT HLS/DSP tutorial uses the embedded processing system (PS) as an external controller to control the 2D-FFT and data mover PL kernels. Review the [Programming the PS Host Application](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) section in the documentation to understand the process to create a host application. The PS host application (`fft_2d_hls_app.cpp`) is cross-compiled to get the executable. The steps in the tutorial to run the A72 application are as follows. @@ -1496,7 +1496,7 @@ data_transfer_trace=fine trace_buffer_size=500M ``` - For more information, refer to the [xrt.ini](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/xrt.ini-File) documentation. + For more information, refer to the [xrt.ini](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/xrt.ini-File) documentation. 2. After execution on the board, transfer the generated `device_trace_0.csv`, `hal_host_trace.csv`, and `xrt.run_summary` files back to your system. diff --git a/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/README.md b/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/README.md index 1776c1f4da..73b627b904 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/06-fft2d_AIEvsHLS/README.md @@ -137,7 +137,7 @@ fft2d_AIEvsHLS * [AI Engine Development Design Process](https://www.xilinx.com/support/documentation-navigation/design-process/ai-engine-development.html) -* [AM011 AI Engine Architecture Manual](https://docs.xilinx.com/r/en-US/am011-versal-acap-trm) +* [AM011 AI Engine Architecture Manual](https://docs.amd.com/r/en-US/am011-versal-acap-trm) * [Versal ACAP AI Engines for Dummies](https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-ACAP-AI-Engines-for-Dummies/ba-p/1132493) @@ -158,11 +158,11 @@ To build and run the 2D-FFT tutorial (AI Engine and HLS implementations), perfor * Obtain licenses for AI Engine tools. -* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT). +* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT). * Download and set up the [VCK190 Vitis Platform](https://www.xilinx.com/member/vck190_headstart.html#docs). -* [DSP Library(DSPLIB) Documentation](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/index.html) +* [DSP Library(DSPLIB) Documentation](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/index.html) * Download the [DSP Library] (https://github.com/Xilinx/Vitis_Libraries/tree/master/dsp) @@ -173,7 +173,7 @@ To build and run the 2D-FFT tutorial (AI Engine and HLS implementations), perfor ### Platform -Before beginning the tutorial, make sure you have read and followed the [Vitis Software Platform Release Notes (v2023.2)](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Release-Notes) for setting up software and installing the VCK190 base platform. +Before beginning the tutorial, make sure you have read and followed the [Vitis Software Platform Release Notes (v2023.2)](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Release-Notes) for setting up software and installing the VCK190 base platform. This tutorial targets the [VCK190 production board](https://www.xilinx.com/products/boards-and-kits/vck190.html). If you have already purchased this board, download the necessary files from the lounge and ensure you have the correct licenses installed. If you do not have a board and the required license, contact your AMD sales contact. @@ -265,7 +265,7 @@ These observations give a clear indication of where the AI Engines in Versal can * Reduced latency by ~19.054%. * Moving to AI Engine implementation reduces the PL and DSP resources considerably; 180 DSPs, ~88K FFs, ~56K LUTs, and 250 BRAMs are reduced to 72 AI Engines, 11k FFs, and 3K LUTs. -It is important to understand that those 72 AI Engines are not all required for the 2D-FFT compute: 20 AI Engines/vector cores are required for computation, and 52 AI Engines are required for the memory to store the FFT twiddle factors and also to enable connectivity around the array. The average load on these additional 52 AI Engine tiles is only 79%. This means that if your application needs it, these AI Engines can be shared with other functions to run sequentially, or they can use user constraints to better map and route this function to a reduced number of AI Engine tiles (see [this page](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Mapper/Router-Methodology) for details on the AI Engine mapper/router). +It is important to understand that those 72 AI Engines are not all required for the 2D-FFT compute: 20 AI Engines/vector cores are required for computation, and 52 AI Engines are required for the memory to store the FFT twiddle factors and also to enable connectivity around the array. The average load on these additional 52 AI Engine tiles is only 79%. This means that if your application needs it, these AI Engines can be shared with other functions to run sequentially, or they can use user constraints to better map and route this function to a reduced number of AI Engine tiles (see [this page](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Mapper/Router-Methodology) for details on the AI Engine mapper/router). Additionally, increasing the number of instances in the AI Engine design is easier than the HLS design, which runs into timing closure issues, especially for higher FFT point size designs. @@ -279,13 +279,13 @@ For detailed instructions on taking measurements of the parameters, refer to the ## References -#### [AI Engine Documentation](https://docs.xilinx.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) +#### [AI Engine Documentation](https://docs.amd.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) Contains sections on how to develop AI Engine graphs, how to use the AI Engine compiler, AI Engine simulation, and performance analysis. #### Vitis DSP Libraries -* [Vitis DSP Libraries Comprehensive Documentation](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/index.html) +* [Vitis DSP Libraries Comprehensive Documentation](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/index.html) #### Xilinx Runtime (XRT) Architecture @@ -297,17 +297,17 @@ Below are links to the XRT information used by this tutorial: * [XRT AIE API](https://github.com/Xilinx/XRT/blob/master/src/runtime_src/core/include/experimental/xrt_aie.h): Documents the AI Engine XRT API calls -* [XRT Release Notes](https://docs.xilinx.com/r/en-US/ug1451-xrt-release-notes) +* [XRT Release Notes](https://docs.amd.com/r/en-US/ug1451-xrt-release-notes) -#### Vitis Unified Software Development Platform 2023.2 Documentation (https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation) +#### Vitis Unified Software Development Platform 2023.2 Documentation (https://docs.amd.com/v/u/en-US/ug1416-vitis-documentation) Below are links to Vitis related information referenced in this tutorial: -* [Vitis Application Acceleration Development Flow Documentation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration) +* [Vitis Application Acceleration Development Flow Documentation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration) * [Vitis Application Acceleration Development Flow Tutorials](https://github.com/Xilinx/Vitis-Tutorials) -* [Vitis HLS](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls) +* [Vitis HLS](https://docs.amd.com/r/en-US/ug1399-vitis-hls) ## Known Issues diff --git a/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/AIE/README.md b/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/AIE/README.md index 9fecf933b7..7b5a024496 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/AIE/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/AIE/README.md @@ -1,4 +1,4 @@ - +
@@ -172,7 +172,7 @@ Summary of the switches used: |--kernel \\|-k \|Compile only the specified kernel from the input file. Only one -k option is allowed per Vitis compiler command.| |--output \| -o|Specifies the name of the output file generated by the `v++` command. Ensure that the compilation process output name ends with the XO file suffix.| -[Detailed Description of All Vitis Compiler Switches](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +[Detailed Description of All Vitis Compiler Switches](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) |Input|Description| | --- | --- | @@ -235,8 +235,8 @@ Summary of the switches used: |--pl-freq=\|Specifies the interface frequency (in MHz) for all PLIOs. The default frequency is a quarter of the AI Engine frequency and the maximum supported frequency is half of the AI Engine frequency. The PL frequency specific to each interface is provided in the graph.| |--verbose|Verbose output of the AI Engine compiler emits compiler messages at various stages of compilation. These debug and tracing logs provide useful messages regarding the compilation process.| -[AI Engine Compiler Options](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/AI-Engine-Compiler-Options) -[AI Engine Programming Environment Documentation](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment) +[AI Engine Compiler Options](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/AI-Engine-Compiler-Options) +[AI Engine Programming Environment Documentation](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment) |Inputs Sources|Description| | --- | --- | @@ -308,11 +308,11 @@ Summary of the switches used: |--config |Specifies a configuration file containing `v++` switches.| |--target \| -t [hw\|hw_emu]|Specifies the build target.| |--output \| -o|Specifies the name of the output file generated by the `v++` command. The linking process output file name must end with the .xsa suffix| -|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. [Detailed Profiling Options](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) | -|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. [Detailed Profiling Options](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) | +|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. [Detailed Profiling Options](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) | +|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. [Detailed Profiling Options](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) | -[Detailed Description of All Vitis Compiler Switches](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) -[Linking the Kernels in Vitis](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-System) +[Detailed Description of All Vitis Compiler Switches](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +[Linking the Kernels in Vitis](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-System) |Inputs Sources|Description| | --- | --- | @@ -416,7 +416,7 @@ Summary of the switches used: |-L \|Add directory `` to the list of directories to be searched for -l.| [XRT Documentation](https://xilinx.github.io/XRT/master/html/index.html) -[Details of Host Application Programming](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Host-Programming-for-Bare-Metal) +[Details of Host Application Programming](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Host-Programming-for-Bare-Metal) |Inputs Sources|Description| | --- | --- | @@ -488,8 +488,8 @@ This includes the XRT ini file which includes tracing parameters. |--package.sd_file|Where \ specifies an ELF or other data file to package into the `sd_card` directory/image. This option can be used repeatedly to specify multiple files to add to the `sd_card`.| |--package.defer_aie_run| Load the AI Engine application with the ELF file, but wait to run it until graph run directs it. Required in PS based AI Engine flow.| -[Detailed Desicription of All Vitis Compiler Switches](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) -[Details of Packaging the System](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Packaging) +[Detailed Desicription of All Vitis Compiler Switches](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +[Details of Packaging the System](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Packaging) |Inputs Sources|Description| | --- | --- | @@ -762,7 +762,7 @@ int main(void) { #endif ``` -For more details, refer to the [AI Engine Documentation](https://docs.xilinx.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) for details. +For more details, refer to the [AI Engine Documentation](https://docs.amd.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) for details. Note that for running on the hardware (hw) or hardware emulation (hw_emu), the main() function is not required. In this case, it is only necessary to create an instance of the platform and graph, and the PS Host application code controls it through XRT calls. (See PS Host Application in the following section) @@ -865,7 +865,7 @@ Close the datamover kernel and FIR chain graph. ## References The following documents provide supplemental information for this tutorial. -#### [AI Engine Documentation](https://docs.xilinx.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) +#### [AI Engine Documentation](https://docs.amd.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) Contains sections on how to develop AI Engine graphs, how to use the AI Engine compiler, and AI Engine simulation, and performance analysis. #### Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/HLS/README.md b/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/HLS/README.md index c225f38d8e..3bad9099a9 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/HLS/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/HLS/README.md @@ -1,4 +1,4 @@ -

2024.1 Versal AI Engine/HLS FIR Filter Tutorial (AI Engine Implementation)

+
@@ -168,7 +168,7 @@ Summary of the switches used: |--kernel \\|-k \|Compile only the specified kernel from the input file. Only one -k option is allowed per Vitis compiler command.| |--output \| -o|Specifies the name of the output file generated by the V++ command. The compilation process output name must end with the XO file suffix.| -[Detailed Description of All Vitis Compiler Switches](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +[Detailed Description of All Vitis Compiler Switches](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) |Input|Description| | --- | --- | @@ -247,11 +247,11 @@ Summary of the Switches used: |--config |Specifies a configuration file containing `v++` switches.| |--target \| -t [hw\|hw_emu]|Specifies the build target.| |--output \| -o|Specifies the name of the output file generated by the `v++` command. The linking process output file name must end with the .xsa suffix| -|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. [Detailed Profiling Options](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) | -|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. [Detailed Profiling Options](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) | +|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. [Detailed Profiling Options](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) | +|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. [Detailed Profiling Options](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) | -[Detailed Description of All Vitis Compiler Switches](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) -[Linking the Kernels in Vitis](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-System) +[Detailed Description of All Vitis Compiler Switches](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +[Linking the Kernels in Vitis](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-System) |Inputs Sources|Description| | --- | --- | @@ -312,7 +312,7 @@ Summary of the Switches used: |-L \|Add directory `` to the list of directories to be searched for -l.| [XRT Documentation](https://xilinx.github.io/XRT/master/html/index.html) -[Details of Host Application Programming](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Host-Programming-for-Bare-Metal) +[Details of Host Application Programming](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Host-Programming-for-Bare-Metal) |Inputs Sources|Description| | --- | --- | @@ -379,8 +379,8 @@ This will include the XRT ini file which includes tracing parameters. |--package.sd_file|Where \ specifies an ELF or other data file to package into the `sd_card` directory/image. This option can be used repeatedly to specify multiple files to add to the `sd_card`.| -[Detailed Description of All Vitis Compiler Switches](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) -[Details of Packaging the System](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Packaging) +[Detailed Description of All Vitis Compiler Switches](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +[Details of Packaging the System](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Packaging) |Inputs Sources|Description| | --- | --- | @@ -895,10 +895,10 @@ Close the datamover kernel objects. ## References The following documents provide supplemental information for this tutorial. -#### [AI Engine Documentation](https://docs.xilinx.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) +#### [AI Engine Documentation](https://docs.amd.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) Contains sections on how to develop AI Engine graphs, how to use the AI Engine compiler, AI Engine simulation, and performance analysis. -#### [ FIR Compiler v7.2](https://docs.xilinx.com/r/en-US/pg149-fir-compiler) +#### [ FIR Compiler v7.2](https://docs.amd.com/r/en-US/pg149-fir-compiler) Describes the FIR Compiler IP describes all of the parameters and settings and how they control the final filter implementation. diff --git a/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/README.md b/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/README.md index da341caca7..0651f2f620 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/07-firFilter_AIEvsHLS/README.md @@ -118,7 +118,7 @@ filter_AIEvsHLS * [AI Engine Development Design Process](https://www.xilinx.com/support/documentation-navigation/design-process/ai-engine-development.html) -* [AM009 AI Engine Architecture Manual](https://docs.xilinx.com/r/en-US/am009-versal-ai-engine/Revision-History) +* [AM009 AI Engine Architecture Manual](https://docs.amd.com/r/en-US/am009-versal-ai-engine/Revision-History) * [Versal ACAP AI Engines for Dummies](https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-ACAP-AI-Engines-for-Dummies/ba-p/1132493) @@ -126,7 +126,7 @@ filter_AIEvsHLS * [Versal AI Engines Secure Site](https://www.xilinx.com/member/forms/registration/versal_ai_engines.html#documentation) -* [AI Engine Documentation](https://docs.xilinx.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US) +* [AI Engine Documentation](https://docs.amd.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US)
@@ -137,15 +137,15 @@ filter_AIEvsHLS To build and run the FIR filter tutorial (AI Engine and DSP implementations), install the following tools. -* Install the [Vitis Software Platform 2024.1](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation) +* Install the [Vitis Software Platform 2024.1](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installation) * Obtain licenses for AI Engine tools -* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT) +* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT) * Download and set up the [VCK190 Vitis Platform for 2024.1](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html) -* [DSP Library (DSPLib) Documentation](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/index.html) +* [DSP Library (DSPLib) Documentation](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/index.html) * Download the [DSP Library](https://github.com/Xilinx/Vitis_Libraries/tree/master/dsp) @@ -227,7 +227,7 @@ Typically, one of the first steps of a design is deciding on an architecture and For DSP based design, the designer begins with an estimate of the system clock rate that the PL is capable of, and divides that by the desired filter throughput to determine how many clock cycles can be used to process a sample. By feeding this number into the FIR Compiler, the FIR is constructed with the minimum resources required to implement the design; the higher the clock cycles per sample, the fewer resources used. -For AI Engine based designs, a FIR kernel running on the AI Engine is executing its code at the AI Engine clock rate (which 1 GHz for the platform used). The maximum throughput of various filter configuration has been benchmarked and can be found on the [Vitis DSP Library Benchmark/QoR page](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/user_guide/L2/benchmark.html). +For AI Engine based designs, a FIR kernel running on the AI Engine is executing its code at the AI Engine clock rate (which 1 GHz for the platform used). The maximum throughput of various filter configuration has been benchmarked and can be found on the [Vitis DSP Library Benchmark/QoR page](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/user_guide/L2/benchmark.html). For the filter sizes selected in this tutorial cascade length of 1 and window_size of 2048 , the following AI Engine throughputs are obtained: @@ -451,7 +451,7 @@ Upon analysis, it was observed that the computation efficiency is high in a sing Throughput and Latency Measurements ### Throughput and Latency Measurements -To maintain consistency between the AI Engine and DSP implementation, the same flow to measure throughput is used to run the design in hardware and capture trace data in run time. Refer to the [Vitis Unified Software Development Platform documentation](https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation) for more information. +To maintain consistency between the AI Engine and DSP implementation, the same flow to measure throughput is used to run the design in hardware and capture trace data in run time. Refer to the [Vitis Unified Software Development Platform documentation](https://docs.amd.com/v/u/en-US/ug1416-vitis-documentation) for more information. To setup the flow to measure throughput, refer to the section **Run on Hardware** in the AI Engine and HLS implementation documentation, and run the application. diff --git a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md index e6f99f005c..99be9458b7 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md @@ -126,11 +126,11 @@ make sim * [Packet Switching AI Engine Tutorial](https://github.com/Xilinx/Vitis-Tutorials/tree/master/AI_Engine_Development/Feature_Tutorials/04-packet-switching) -* [AI Engine Documentation - Explicit Packet Switching](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding/Explicit-Packet-Switching) +* [AI Engine Documentation - Explicit Packet Switching](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding/Explicit-Packet-Switching) -* [Compiling an AI Engine Graph Application](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Compiling-an-AI-Engine-Graph-Application) +* [Compiling an AI Engine Graph Application](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Compiling-an-AI-Engine-Graph-Application) -* [Simulating an AI Engine Graph Application](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Simulating-an-AI-Engine-Graph-Application) +* [Simulating an AI Engine Graph Application](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Simulating-an-AI-Engine-Graph-Application) ## Next Steps diff --git a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md index 089cd5e94c..15f0746eeb 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md @@ -93,11 +93,11 @@ The `s2mm_mp` kernel is generated from the `kernel/spec.json` specification. Rev * [Vitis Libraries Github Repo](https://github.com/Xilinx/Vitis_Libraries) -* [Vitis Utilities Library Documentation](https://docs.xilinx.com/r/en-US/Vitis_Libraries/utils/index.html) +* [Vitis Utilities Library Documentation](https://docs.amd.com/r/en-US/Vitis_Libraries/utils/index.html) -* [Generating PL Data-Mover Kernels](https://docs.xilinx.com/r/en-US/Vitis_Libraries/utils/datamover/kernel_gen_guide.html) +* [Generating PL Data-Mover Kernels](https://docs.amd.com/r/en-US/Vitis_Libraries/utils/datamover/kernel_gen_guide.html) -* [Vitis Compiler Command](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +* [Vitis Compiler Command](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) ## Next Steps diff --git a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md index a74b10c0bc..e842e9f813 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md @@ -52,7 +52,7 @@ The following image was taken from the Vivado project for the entire design. It * [Beamforming Tutorial - Module_04 - AI Engine and PL Integration](https://github.com/Xilinx/Vitis-Tutorials/tree/master/AI_Engine_Development/Design_Tutorials/03-beamforming) -* [Vitis Compiler Command](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +* [Vitis Compiler Command](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) ## Next Steps diff --git a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_05_host_sw/README.md b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_05_host_sw/README.md index 4cb3a58bfd..1031fa193e 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_05_host_sw/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_05_host_sw/README.md @@ -1,4 +1,4 @@ -

2024.1 Versal AI Engine/HLS FIR Filter Tutorial (HLS Implementation)

+

AMD Versal™ Adaptive SoC AI Engine Tutorials

See AMD Vitis™ Development Environment on xilinx.com
 @@ -112,8 +112,8 @@ The following is the general execution flow for the host applications. * [XRT Github Repo](https://github.com/Xilinx/XRT) -* [Vitis Developing Application Documentation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Developing-Applications) -* [Vitis Building-and-Running-the-Application Documentation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Building-and-Running-the-Application) +* [Vitis Developing Application Documentation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Developing-Applications) +* [Vitis Building-and-Running-the-Application Documentation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Building-and-Running-the-Application) ## Next Steps After compiling the host software, you are ready to create the sd_card.img and run the design on hardware in the next module, [Module 06 - SD Card and Hardware Run](../Module_06_sd_card_and_hw_run). diff --git a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md index c728597939..3ad8694618 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md @@ -135,7 +135,7 @@ scp animation_data.txt @://Module_07_results/data ## References -* [Vitis Compiler Command](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) +* [Vitis Compiler Command](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) ## Next Steps diff --git a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/README.md b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/README.md index a6fba30ad6..b3a0b3690b 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/08-n-body-simulator/README.md @@ -33,18 +33,18 @@ This tutorial can be run on the [VCK190 Board](https://www.xilinx.com/products/b ### *Documentation*: Explore AI Engine Architecture -* [AM009 AI Engine Architecture Manual](https://docs.xilinx.com/r/en-US/am009-versal-ai-engine/Revision-History) +* [AM009 AI Engine Architecture Manual](https://docs.amd.com/r/en-US/am009-versal-ai-engine/Revision-History) -* [AI Engine Documentation](https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation) +* [AI Engine Documentation](https://docs.amd.com/v/u/en-US/ug1416-vitis-documentation) ### *Tools*: Installing the Tools 1. Obtain a license to enable beta devices in AMD tools (to use the VCK190 platform). 2. Obtain licenses for AI Engine tools. -3. Follow the instructions for the [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) and ensure you have the following tools: +3. Follow the instructions for the [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) and ensure you have the following tools: - * [Vitis™ Unified Software Development Platform 2024.1](https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation) - * [Xilinx® Runtime and Platforms (XRT)](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) + * [Vitis™ Unified Software Development Platform 2024.1](https://docs.amd.com/v/u/en-US/ug1416-vitis-documentation) + * [Xilinx® Runtime and Platforms (XRT)](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) * [Embedded Platform VCK190 Base or VCK190 ES1 Base](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html) ### *Environment*: Setting Up Your Shell Environment @@ -93,7 +93,7 @@ The goal of this tutorial is to create a general-purpose floating point accelera |AI Engine N-Body SImulator|Versal AI Engine IP|O(N)|0.007| ### PL Data-Mover Kernels -Another goal of this tutorial is to showcase how to generate PL Data-Mover kernels from the [AMD Vitis Utility Library](https://docs.xilinx.com/r/en-US/Vitis_Libraries/utils/datamover/kernel_gen_guide.html). These kernels moves any amount of data from DDR buffers to AXI-Streams. +Another goal of this tutorial is to showcase how to generate PL Data-Mover kernels from the [AMD Vitis Utility Library](https://docs.amd.com/r/en-US/Vitis_Libraries/utils/datamover/kernel_gen_guide.html). These kernels moves any amount of data from DDR buffers to AXI-Streams. ## The N-Body Problem The N-Body problem is the problem of predicting the motions of a group of N objects which each have a gravitational force on each other. For any particle `i` in the system, the summation of the gravitational forces from all the other particles results in the acceleration of particle `i`. From this acceleration, we can calculate a particle's velocity and position (`x y z vx vy vz`) will be in the next timestep. Newtonian physics describes the behavior of very large bodies/particles within our universe. With certain assumptions, the laws can be applied to bodies/particles ranging from astronomical size to a golf ball (and even smaller). diff --git a/AI_Engine_Development/AIE/Design_Tutorials/09-ddc_chain/README.md b/AI_Engine_Development/AIE/Design_Tutorials/09-ddc_chain/README.md index 10d2f5f896..8ea34d42d5 100644 --- a/AI_Engine_Development/AIE/Design_Tutorials/09-ddc_chain/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/09-ddc_chain/README.md @@ -1,4 +1,4 @@ - @@ -51,7 +51,7 @@ This tutorial demonstrates the steps to upgrade a 32-branch digital down-convers - Updating older pragmas - Supporting x86 compilation and simulation -You can find the design description in the [Digital Down-conversion Chain Implementation on AI Engine (XAPP1351)](https://docs.xilinx.com/r/en-US/xapp1351-ddc-ai-engine). The codebase associated with the original design can be found in the [Reference Design Files](https://www.xilinx.com/cgi-bin/docs/ctdoc?cid=d3643c02-32f7-407c-b680-59c0b234e703;d=xapp1352-beamforming-ai-engine.zip). +You can find the design description in the [Digital Down-conversion Chain Implementation on AI Engine (XAPP1351)](https://docs.amd.com/r/en-US/xapp1351-ddc-ai-engine). The codebase associated with the original design can be found in the [Reference Design Files](https://www.xilinx.com/cgi-bin/docs/ctdoc?cid=d3643c02-32f7-407c-b680-59c0b234e703;d=xapp1352-beamforming-ai-engine.zip). ## Upgrading Tools, Device Speed Grade, and Makefile @@ -90,7 +90,7 @@ When creating the kernel in the upper graph or subgraph, use `kernel::create_obj ### Migrating from Windows to Buffers -Windows I/O connections between kernels were deprecated in the 2023.2 release of the AMD Vitis™ software platform. The AI Engine Kernel and Graph Programming Guide [(UG1079)](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding/Comparison-between-Buffer-Ports-and-Windows) describes how the source code of a design should change to upgrade it to buffer I/Os. The following figures show the steps required (repeated for every kernel) to upgrade I/O connections from Windows to buffers. +Windows I/O connections between kernels were deprecated in the 2023.2 release of the AMD Vitis™ software platform. The AI Engine Kernel and Graph Programming Guide [(UG1079)](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding/Comparison-between-Buffer-Ports-and-Windows) describes how the source code of a design should change to upgrade it to buffer I/Os. The following figures show the steps required (repeated for every kernel) to upgrade I/O connections from Windows to buffers. 1. Make the changes shown in the following figure in the ``kernel.cc`` file: @@ -116,7 +116,7 @@ The following example shows a side-by-side comparison of intrinsic-based code co ### Handling State Variables to Enable x86sim -Move the state variables instantiation from ``kernel::run`` to class member or use ``thread_local``, as shown below. More information can be found in the in Memory Model section of the AI Engine Tools and Flows User Guide [(UG1076)](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Memory-Model). +Move the state variables instantiation from ``kernel::run`` to class member or use ``thread_local``, as shown below. More information can be found in the in Memory Model section of the AI Engine Tools and Flows User Guide [(UG1076)](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Memory-Model). ![figure11](images/handling_state_variables_x86sim.png) diff --git a/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/AIE/README.md b/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/AIE/README.md index 80549819b5..3c5ed72dca 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/AIE/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/AIE/README.md @@ -1,4 +1,4 @@ - +
@@ -24,7 +24,7 @@ ### Design Build -In this section, you build and run the GeMM design using the AI Engine implementation. You compile the AI Engine design and integrate it into a larger system design (including the PL kernels and PS host application). Review the [Integrating the Application section in the AI Engine Documentation](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow) for the general flow. +In this section, you build and run the GeMM design using the AI Engine implementation. You compile the AI Engine design and integrate it into a larger system design (including the PL kernels and PS host application). Review the [Integrating the Application section in the AI Engine Documentation](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Integrating-the-Application-Using-the-Vitis-Tools-Flow) for the general flow. At the end of this section, the design flow will generate a new directory (called `build/`). Underneath are sub-directories named `(gemm_$(MAT_DIMS)/` (for example, `gemm_32x32x32/`) depending on the Mat A and Mat B dimensions and the number of instances `x$(GEMM_INSTS)` chosen in the build. Each sub-directory contains the `hw_emu/` and/or `hw/` subfolders. The respective subfolders contain `Work/` and `libadf.a`, outputs from the AI Engine compiler, the host app executable and the builds, targeted to `hw` or `hw_emu` respectively. The `hw_emu/` subfolder contains the build for hardware emulation. The `hw/` subfolder contains the build for hardware run on a VCK190 board. @@ -138,7 +138,7 @@ $(BUILD_TARGET_DIR)/$(DATAMOVER_KERNEL_XO).xo: $(DATAMOVER_KERNEL_SRC) -o $@ ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) for a detailed description of all Vitis compiler switches. The following table provides a summary of the switches used. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) for a detailed description of all Vitis compiler switches. The following table provides a summary of the switches used. |Switch|Description| | --- | --- | @@ -222,7 +222,7 @@ $(LIBADF_A): $(AIE_SRC_REPO)/graph.* aiecompiler $(AIE_FLAGS) $(GRAPH_SRC_CPP) 2>&1 | tee -a aiecompiler.log ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment) for full AI Engine programming environment documentation. +See [this page](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment) for full AI Engine programming environment documentation. The following table provides a summary of the switches used. @@ -302,7 +302,7 @@ $(BUILD_TARGET_DIR)/$(XSA):$(KERNEL_XOS) $(SYSTEM_CONFIGS_REPO)/* cd $(BUILD_TARGET_DIR); \ v++ -l $(VPP_FLAGS) $(VPP_LINK_FLAGS) -t $(TARGET) -o $@ $(KERNEL_XOS) $(LIBADF_A) ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Device-Binary) for a detailed description of Vitis linking options. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Device-Binary) for a detailed description of Vitis linking options. |Switch|Description| | --- | --- | @@ -312,8 +312,8 @@ See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceler |--verbose|Display verbose/debug information.| |--config |Specifies a configuration file containing V++ switches.| |--output \| -o|Specifies the name of the output file generated by the V++ command. In this design the outputs of the DMA HLS kernels and the PL kernels interfacing with the AI Engine are in XO files.| -|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| -|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| +|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| +|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| The information to tell the linker how to connect the AI Engine and PL kernels together is described in a configuration file, `system_configs/x$(GEMM_INSTS).cfg`. The file describes the overall connection scheme of the system. @@ -369,7 +369,7 @@ param=hw_emu.enableProfiling=false ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) for a detailed description of the Vitis compiler configuration file. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) for a detailed description of the Vitis compiler configuration file. |Switch|Comment| | --- | --- | @@ -410,7 +410,7 @@ $(BUILD_TARGET_DIR)/$(APP_ELF): $(HOST_APP_SRC)/* $(LIBADF_A) ``` -See [this page](https://xilinx.github.io/XRT/master/html/index.html) for XRT documentation. See [this page](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) for details of host application programming. +See [this page](https://xilinx.github.io/XRT/master/html/index.html) for XRT documentation. See [this page](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) for details of host application programming. @@ -495,14 +495,14 @@ $(EMBEDDED_PACKAGE_OUT): $(PROFILING_CONFIGS_REPO)/* $(EXEC_SCRIPTS_REPO)/* $(BU v++ -p $(PKG_FLAGS) ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/package-Options) for more details about packaging the system. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/package-Options) for more details about packaging the system. |Switch|Description| | --- | --- | |--target \| -t [hw\|hw_emu]|Specifies the build target.| |--package \| -p|Packages the final product at the end of the Vitis compile and link build process.| -|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) for more information.| -|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) for more information.| +|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) for more information.| +|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) for more information.| |--package.boot_mode \|Where \ specifies . Boot mode used for running the application in emulation or on hardware.| |--package.image_format|Where \ specifies the \ output image file format. `ext4` is the Linux file system and `fat32` is the Windows file system.| |--package.sd_file|Where \ specifies an ELF or other data file to package into the `sd_card` directory/image. This option can be used repeatedly to specify multiple files to add to the `sd_card` directory.| @@ -870,7 +870,7 @@ The streaming interface data width is kept at 128 bits to reduce read/write over ### AI Engine Kernels and Graph Representation -An AI Engine kernel is a C/C++ program written using specialized intrinsic calls that target the VLIW vector processor. The AI Engine compiler compiles the kernel code to produce an executable ELF file for each of the AI Engines being used in the design. Review the [AI Engine Kernel Programming](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding) section in the AI Engine documentation for a high-level overview of kernel programming. These kernels can be stitched together to function as AI Engine graphs written in C++. In this design, the AI Engine compiler writes a summary of compilation results. You can view the graph by running the following command: +An AI Engine kernel is a C/C++ program written using specialized intrinsic calls that target the VLIW vector processor. The AI Engine compiler compiles the kernel code to produce an executable ELF file for each of the AI Engines being used in the design. Review the [AI Engine Kernel Programming](https://docs.amd.com/r/en-US/ug1079-ai-engine-kernel-coding) section in the AI Engine documentation for a high-level overview of kernel programming. These kernels can be stitched together to function as AI Engine graphs written in C++. In this design, the AI Engine compiler writes a summary of compilation results. You can view the graph by running the following command: `vitis_analyzer $(BUILD_TARGET_DIR)/Work/graph.aiecompile_summary` @@ -892,7 +892,7 @@ The overall graph definition of the design is contained in the `graph.cpp` file. #### Defining the Graph Class -Define the graph classes by using the objects defined in the appropriate name space. It must include the ADF library and [Vitis DSP Library](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/user_guide/L2/dsp-lib-func.html#matrix-multiply) for GeMM. A general specification is put in for the ADF namespace: +Define the graph classes by using the objects defined in the appropriate name space. It must include the ADF library and [Vitis DSP Library](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/user_guide/L2/dsp-lib-func.html#matrix-multiply) for GeMM. A general specification is put in for the ADF namespace: ``` @@ -1183,14 +1183,14 @@ int dma_hls( } ``` -The `dma_hls` kernel also specifies HLS pragmas to help optimize the kernel code and adhere to interface protocols. See [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas) for detailed documentation of all HLS pragmas. A summary of the HLS pragmas used in the kernel is provided in the following table. +The `dma_hls` kernel also specifies HLS pragmas to help optimize the kernel code and adhere to interface protocols. See [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas) for detailed documentation of all HLS pragmas. A summary of the HLS pragmas used in the kernel is provided in the following table. |Switch|Description| | --- | --- | -|#pragma HLS INTERFACE|In C/C++ code, all input and output operations are performed, in zero time, through formal function arguments. In a RTL design, these same input and output operations must be performed through a port in the design interface and typically operate using a specific input/output (I/O) protocol. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-interface).| -|#pragma HLS PIPELINE II=1|Reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the config_compile -pipeline_style command, but can be overridden in the PIPELINE pragma or directive. For more information, see [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline).| -|#pragma HLS dataflow|The DATAFLOW pragma enables task-level pipelining, allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and increasing the overall throughput of the design. See [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow) for more information.| -|#pragma HLS loop_tripcount|When manually applied to a loop, specifies the total number of iterations performed by a loop. The `LOOP_TRIPCOUNT` pragma or directive is for analysis only, and does not impact the results of synthesis. See [this page](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-loop_tripcount) for more information.| +|#pragma HLS INTERFACE|In C/C++ code, all input and output operations are performed, in zero time, through formal function arguments. In a RTL design, these same input and output operations must be performed through a port in the design interface and typically operate using a specific input/output (I/O) protocol. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-interface).| +|#pragma HLS PIPELINE II=1|Reduces the initiation interval (II) for a function or loop by allowing the concurrent execution of operations. The default type of pipeline is defined by the config_compile -pipeline_style command, but can be overridden in the PIPELINE pragma or directive. For more information, see [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline).| +|#pragma HLS dataflow|The DATAFLOW pragma enables task-level pipelining, allowing functions and loops to overlap in their operation, increasing the concurrency of the RTL implementation and increasing the overall throughput of the design. See [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-dataflow) for more information.| +|#pragma HLS loop_tripcount|When manually applied to a loop, specifies the total number of iterations performed by a loop. The `LOOP_TRIPCOUNT` pragma or directive is for analysis only, and does not impact the results of synthesis. See [this page](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-loop_tripcount) for more information.| @@ -1199,7 +1199,7 @@ The `dma_hls` kernel also specifies HLS pragmas to help optimize the kernel code ### PS Host Application -The GeMM AI Engine tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine graph and data mover PL kernels. Review the [Programming the PS Host Application](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) section in the AI Engine documentation to understand the process to create a host application. +The GeMM AI Engine tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine graph and data mover PL kernels. Review the [Programming the PS Host Application](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) section in the AI Engine documentation to understand the process to create a host application. In addition to the PS host application (`gemm_aie_app.cpp`), the AI Engine control code must also be compiled. This control code (`aie_control_xrt.cpp`) is generated by the AI Engine compiler when compiling the AI Engine design graph and kernel code. The AI Engine control code is used by the PS host application for the following purposes: @@ -1400,7 +1400,7 @@ Throughput is measured in mega-samples transferred per second (MSPS). Latency is trace_buffer_size=500M ``` - Refer to the [xrt.ini](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/xrt.ini-File) documentation for more information. + Refer to the [xrt.ini](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/xrt.ini-File) documentation for more information. 2. After execution on the board, transfer the generated `device_trace_0.csv`, `hal_host_trace.csv`, and `xrt.run_summary` files back to your system. diff --git a/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/DSP/README.md b/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/DSP/README.md index c5bc887a8a..2cb8d4cea7 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/DSP/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/DSP/README.md @@ -1,4 +1,4 @@ -

2024.1 Versal GeMM Implementation Using Vitis Acceleration Library Tutorial

+
@@ -97,7 +97,7 @@ The generated files are placed under an individual directory: `$(BUILD_TARGET_DI
-See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) for a detailed description of all Vitis compiler switches. The following table provides a summary of the switches used. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/v-Command) for a detailed description of all Vitis compiler switches. The following table provides a summary of the switches used. |Switch|Description| @@ -188,7 +188,7 @@ v++ -l --platform xilinx_vck190_base_202410_1 --save-temps --temp_dir $(BUILD_TA -t hw_emu -o $(BUILD_TARGET_DIR)/gemm.hw_emu.xclbin $(PROJECT_REPO)/build/gemm_GEMM_SIZExGEMM_SIZExGEMM_SIZE/gemm_large_ocm.xo ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Device-Binary) for a detailed description of Vitis linking options. The following table provides a summary of the switches used. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Device-Binary) for a detailed description of Vitis linking options. The following table provides a summary of the switches used. |Switch|Description| | --- | --- | @@ -197,9 +197,9 @@ See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceler |--temp_dir |This allows you to manage the location where the tool writes temporary files created during the build process. The temporary results are written by the Vitis compiler, and then removed, unless the `--save-temps` option is also specified.| |--verbose|Display verbose/debug information.| |--output \| -o|Specifies the name of the output file generated by the V++ command. In this design the outputs of the HLS/DSP kernels with their interfacing with the PL kernels are in XO files.| -|--vivado.prop \|Specifies properties for the Vivado Design Suite to be used during synthesis and implementation of the FPGA binary (xclbin). See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/vivado-Options) for detailed Vivado options.| -|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| -|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| +|--vivado.prop \|Specifies properties for the Vivado Design Suite to be used during synthesis and implementation of the FPGA binary (xclbin). See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/vivado-Options) for detailed Vivado options.| +|--profile.data [\|all]:[\|all]:[\|all]\(:[counters\|all]\)|Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| +|--profile.trace_memory \:\\|\[\]|When building the hardware target \(-t=hw\), use this option to specify the type and amount of memory to use for capturing trace data. See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/profile-Options) for detailed profiling options.| |--config |Specifies a configuration file containing V++ switches.| The information to tell the linker how to connect the PL kernels together is described in a configuration file, `system_configs/gemm.cfg`. The file describes the overall connection scheme of the system. @@ -228,7 +228,7 @@ prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=AggressiveExplore ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) for a detailed description of the Vitis compiler configuration file. A summary of the configuration options used is provided in the following table. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Configuration-File) for a detailed description of the Vitis compiler configuration file. A summary of the configuration options used is provided in the following table. |Switch|Comment| @@ -281,7 +281,7 @@ aarch64-xilinx-linux-g++ -mcpu=cortex-a72.cortex-a53 -march=armv8-a+crc -fstack ``` -See [this page](https://xilinx.github.io/XRT/master/html/index.html) for XRT documentation. See [this page](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) for details of host application programming. +See [this page](https://xilinx.github.io/XRT/master/html/index.html) for XRT documentation. See [this page](https://docs.amd.com/r/en-US/ug1076-ai-engine-environment/Programming-the-PS-Host-Application) for details of host application programming. |Switch|Description| @@ -343,15 +343,15 @@ If the `XRT_ROOT` is set, the following Vitis compiler flags are also set: --package.sd_dir $(XRT_ROOT) ``` -See [this page](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/package-Options) for more details about packaging the system. +See [this page](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/package-Options) for more details about packaging the system. |Switch|Description| | --- | --- | |--target \| -t [hw\|hw_emu]|Specifies the build target.| |--package \| -p|Packages the final product at the end of the Vitis compile and link build process.| -|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) for more information.| -|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) for more information.| +|--package.rootfs \|Where \ specifies the absolute or relative path to a processed Linux root file system file. The platform RootFS file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) for more information.| +|--package.kernel_image \|Where \ specifies the absolute or relative path to a Linux kernel image file. Overrides the existing image available in the platform. The platform image file is available for download from xilinx.com. Refer to the [Vitis Software Platform Installation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Installation) for more information.| |--package.boot_mode \|Where \ specifies Boot mode used for running the application in emulation or on hardware.| |--package.image_format|Where \ specifies \ output image file format. `ext4` is the Linux file system and `fat32` is the Windows file system.| |--package.sd_file|Where \ specifies an ELF or other data file to package into the `sd_card` directory/image. This option can be used repeatedly to specify multiple files to add to the `sd_card`.| @@ -638,7 +638,7 @@ The `gemm_large_ocm` kernel operates at 700 MHz For timing closure of the whole design, different implementation properties are used, as mentioned in the `make xsa` step above. These strategies are required because timing is not met for default implementation settings. Routing Congestion limits operating frequency to 700MHz. -For more information about implementation strategies, see the _Vivado Implementation User Guide_ [UG904](https://docs.xilinx.com/r/en-US/ug904-vivado-implementation) +For more information about implementation strategies, see the _Vivado Implementation User Guide_ [UG904](https://docs.amd.com/r/en-US/ug904-vivado-implementation) ### Data Flow diff --git a/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/README.md b/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/README.md index 89c24ed024..6837da0878 100755 --- a/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/10-GeMM_AIEvsDSP/README.md @@ -127,7 +127,7 @@ GeMM_AIEvsDSP * [AI Engine Development Design Process](https://www.xilinx.com/support/documentation-navigation/design-process/ai-engine-development.html) -* [AM009 AI Engine Architecture Manual](https://docs.xilinx.com/r/en-US/am009-versal-ai-engine/Revision-History) +* [AM009 AI Engine Architecture Manual](https://docs.amd.com/r/en-US/am009-versal-ai-engine/Revision-History) * [Versal ACAP AI Engines for Dummies](https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-ACAP-AI-Engines-for-Dummies/ba-p/1132493) @@ -148,7 +148,7 @@ To build and run the GeMM tutorial (AI Engine and HLS implementations), perform * Obtain licenses for AI Engine tools. -* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT). +* Follow the instructions in [Installing Xilinx Runtime and Platforms](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Xilinx-Runtime-and-Platforms) (XRT). * Download and set up the [VCK190 Vitis Platform]( https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html). @@ -159,7 +159,7 @@ To build and run the GeMM tutorial (AI Engine and HLS implementations), perform ### Platform -Before beginning the tutorial, make sure you have read and followed the [Vitis Software Platform Release Notes (v2023.2)](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Release-Notes) for setting up software and installing the VCK190 base platform. +Before beginning the tutorial, make sure you have read and followed the [Vitis Software Platform Release Notes (v2023.2)](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Software-Platform-Release-Notes) for setting up software and installing the VCK190 base platform. This tutorial targets the [VCK190 production board](https://www.xilinx.com/products/boards-and-kits/vck190.html). If you have already purchased this board, download the necessary files from the lounge and ensure you have the correct licenses installed. If you do not have a board and the required license, contact your AMD sales team. @@ -259,13 +259,13 @@ For detailed instructions on taking measurements of the parameters, refer to the ## References -#### [Vitis Unified Software Development Platform Documentation](https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation) +#### [Vitis Unified Software Development Platform Documentation](https://docs.amd.com/v/u/en-US/ug1416-vitis-documentation) Contains sections on how to develop AI Engine graphs, how to use the AI Engine compiler and AI Engine simulation, and performance analysis. #### [Vitis DSP Libraries](https://github.com/Xilinx/Vitis_Libraries/tree/master/dsp) -* [Vitis DSP Libraries Comprehensive Documentation](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/index.html) +* [Vitis DSP Libraries Comprehensive Documentation](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/index.html) #### [Xilinx Runtime (XRT) Architecture](https://xilinx.github.io/XRT/master/html/index.html) @@ -281,16 +281,16 @@ Below are links to the XRT information used by this tutorial: * [XRT Release Notes](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2023_2/ug1451-xrt-release-notes.pdf) -#### [Vitis Unified Software Development Platform 2023.2 Documentation](https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation) +#### [Vitis Unified Software Development Platform 2023.2 Documentation](https://docs.amd.com/v/u/en-US/ug1416-vitis-documentation) Below are links to Vitis related information referenced in this tutorial: -* [Vitis Application Acceleration Development Flow Documentation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration) +* [Vitis Application Acceleration Development Flow Documentation](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration) * [Vitis Application Acceleration Development Flow Tutorials](https://github.com/Xilinx/Vitis-Tutorials) -* [Vitis HLS](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls) +* [Vitis HLS](https://docs.amd.com/r/en-US/ug1399-vitis-hls) ## Known Issues diff --git a/AI_Engine_Development/AIE/Design_Tutorials/12-IFFT64K-2D/README.md b/AI_Engine_Development/AIE/Design_Tutorials/12-IFFT64K-2D/README.md index 0f4cde210f..5848925629 100644 --- a/AI_Engine_Development/AIE/Design_Tutorials/12-IFFT64K-2D/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/12-IFFT64K-2D/README.md @@ -1,4 +1,4 @@ - +

2024.1 Versal Matrix Multiplication using DSP58 Tutorial (XDXX)

AI Engine Development

@@ -28,11 +28,11 @@ ## Introduction -The [Vitis DSP Library](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/index.html) currently implements the Fast Fourier Transform (FFT) using a Stockham algorithm. This algorithm computes the transform using a pair of buffers rather than the more popular in-place Cooley-Tukey approach, and maps more efficiently to the vector/SIMD architecture of the AI Engine. This approach yields excellent results, particularly for $N < 4096$ where the processing and storage requirements may be serviced by a single tile. In higher performance cases where sampling rates exceed 1 Gsps (ie. the SSR > 1 regime), this Stockham approach continues to be feasible but leads to an excessive use of tile resources. A more efficient approach is needed for these high throughput use cases. +The [Vitis DSP Library](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/index.html) currently implements the Fast Fourier Transform (FFT) using a Stockham algorithm. This algorithm computes the transform using a pair of buffers rather than the more popular in-place Cooley-Tukey approach, and maps more efficiently to the vector/SIMD architecture of the AI Engine. This approach yields excellent results, particularly for $N < 4096$ where the processing and storage requirements may be serviced by a single tile. In higher performance cases where sampling rates exceed 1 Gsps (ie. the SSR > 1 regime), this Stockham approach continues to be feasible but leads to an excessive use of tile resources. A more efficient approach is needed for these high throughput use cases. A 1D FFT may be implemented on the AI Engine array using a 2D FFT algorithm with higher efficiency overall. This alternative "divide & conquer" approach provides a better solution on the AI Engine array since it is less reliant on "butterfly routing" and we can break large $N$ point sizes into much smaller factors of size $\sqrt N$. This results in a significant reduction in AI Engine tile memory and overall usage of fewer compute tiles. -The 2D architecture is not new to AI Engine. [XAPP1356](https://docs.xilinx.com/r/en-US/xapp1356-fft-ai-engine) first explored its use several years ago to achieve 3.7 Gsps with 10 AI Engine tiles. In this tutorial, we explore using the 2D architecture to implement large point transforms in the SSR > 1 regime: specifically a 64K-pt IFFT @ 2 Gsps. In this scenario, the design requires both AI Engine tile resources for compute and programmable logic (PL) resources for sample reordering as shown in detail below. +The 2D architecture is not new to AI Engine. [XAPP1356](https://docs.amd.com/r/en-US/xapp1356-fft-ai-engine) first explored its use several years ago to achieve 3.7 Gsps with 10 AI Engine tiles. In this tutorial, we explore using the 2D architecture to implement large point transforms in the SSR > 1 regime: specifically a 64K-pt IFFT @ 2 Gsps. In this scenario, the design requires both AI Engine tile resources for compute and programmable logic (PL) resources for sample reordering as shown in detail below. ## Matlab Model A Matlab model of the 64K-pt IFFT implemented as a $256 \times 256$ 2D architecture is shown below. The model & algorithm consist of the following steps: @@ -165,9 +165,9 @@ The build process will generate the SD card image in the ```/12- ## References -[1]: [Vitis DSP Library](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/index.html) +[1]: [Vitis DSP Library](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/index.html) -[2]: [XAPP1356: "Block-by-Block Configurable Fast Fourier Transform Implementation on AI Engine](https://docs.xilinx.com/r/en-US/xapp1356-fft-ai-engine) +[2]: [XAPP1356: "Block-by-Block Configurable Fast Fourier Transform Implementation on AI Engine](https://docs.amd.com/r/en-US/xapp1356-fft-ai-engine) ## Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/13-FFT-DFT-on-AIE/README.md b/AI_Engine_Development/AIE/Design_Tutorials/13-FFT-DFT-on-AIE/README.md index a310624575..51424198f3 100644 --- a/AI_Engine_Development/AIE/Design_Tutorials/13-FFT-DFT-on-AIE/README.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/13-FFT-DFT-on-AIE/README.md @@ -1,4 +1,4 @@ - +

AI Engine Development

@@ -32,10 +32,10 @@ DFT using vector-matrix multiplication that can be efficient on AI Engine for sm ## References 1. [The Fast Fourier Transform](https://ieeexplore.ieee.org/abstract/document/5217220) -2. [Vitis Libraries](https://docs.xilinx.com/r/en-US/Vitis_Libraries/dsp/index.html) +2. [Vitis Libraries](https://docs.amd.com/r/en-US/Vitis_Libraries/dsp/index.html) 3. [UG1529: AI Engine API User Guide](https://www.xilinx.com/htmldocs/xilinx2023_2/aiengine_api/aie_api/doc/index.html) 4. [Fast Computation of General Fourier Transforms on GPUs](https://ieeexplore.ieee.org/document/4607357) -5. [Block-by-Block Configurable Fast Fourier Transform Implementation on AI Engine (XAPP1356)](https://docs.xilinx.com/r/en-US/xapp1356-fft-ai-engine/Summary) +5. [Block-by-Block Configurable Fast Fourier Transform Implementation on AI Engine (XAPP1356)](https://docs.amd.com/r/en-US/xapp1356-fft-ai-engine/Summary) ## Support diff --git a/AI_Engine_Development/AIE/Design_Tutorials/13-FFT-DFT-on-AIE/md/fft-aie.md b/AI_Engine_Development/AIE/Design_Tutorials/13-FFT-DFT-on-AIE/md/fft-aie.md index b7e2d12faa..68848150b0 100644 --- a/AI_Engine_Development/AIE/Design_Tutorials/13-FFT-DFT-on-AIE/md/fft-aie.md +++ b/AI_Engine_Development/AIE/Design_Tutorials/13-FFT-DFT-on-AIE/md/fft-aie.md @@ -1,4 +1,4 @@ - [GH_Getting_started_VHLS]: https://github.com/Xilinx/Vitis-Tutorials/tree/2023.2/Getting_Started/Vitis_HLS -[VHLS_UG1399]: https://docs.xilinx.com/r/en-US/ug1399-vitis-hls +[VHLS_UG1399]: https://docs.amd.com/r/en-US/ug1399-vitis-hls
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md index 2a9410f7ba..0884e3631e 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md @@ -1,4 +1,4 @@ - +

Vitis™ Platform Creation Tutorials

See Vitis™ Development Environment on xilinx.com
 @@ -71,10 +71,10 @@ The platform creation steps are introduced in the following pages. Each page des ## References -- *Vitis Unified Software Platform Documentation: Application Acceleration Development* ([UG1393](https://docs.xilinx.com/access/sources/dita/map?Doc_Version=2023.2%20English&url=ug1393-vitis-application-acceleration)) - - [Platform Creation General Rules](https://docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1393-vitis-application-acceleration&resourceid=vcm1596051749044.html) - - [Setting Up the Vitis Environment](https://docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1393-vitis-application-acceleration&resourceid=zks1565446519267.html) - - [Installing Xilinx Runtime](https://docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1393-vitis-application-acceleration&resourceid=pjr1542153622642.html) +- *Vitis Unified Software Platform Documentation: Application Acceleration Development* ([UG1393](https://docs.amd.com/access/sources/dita/map?Doc_Version=2023.2%20English&url=ug1393-vitis-application-acceleration)) + - [Platform Creation General Rules](https://docs.amd.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1393-vitis-application-acceleration&resourceid=vcm1596051749044.html) + - [Setting Up the Vitis Environment](https://docs.amd.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1393-vitis-application-acceleration&resourceid=zks1565446519267.html) + - [Installing Xilinx Runtime](https://docs.amd.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1393-vitis-application-acceleration&resourceid=pjr1542153622642.html) - Platform Examples - [zcu102](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.2/Xilinx_Official_Platforms/xilinx_zcu102_base) and [zcu104](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.2/Xilinx_Official_Platforms/xilinx_zcu104_base) base platform source code in [Vitis Embedded Platform Source Github Repository](https://github.com/Xilinx/Vitis_Embedded_Platform_Source) - [Xilinx Runtime (XRT)](https://xilinx.github.io/XRT/master/html/index.html) diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md index 0054fa668b..1dbf7a31c5 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md @@ -1,4 +1,4 @@ - +

2024.1 Vitis™ Platform Creation Tutorials

See Vitis™ Development Environment on xilinx.com
 @@ -230,7 +230,7 @@ For simple designs, interrupt signals can be sourced by processor's **pl_ps_irq* Next, we will use the example of modifying the interrupt controller IP address to illustrate how to modify the IP address in the address editor. - - As the interrupt controller is connected with **M_AXI_HPM0_LPD** domain, we need check LPD domain supported address space. Please check the [ZYNQMP Technical Reference Manual](https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PL-AXI-Interface). You could find following address range. That means the IP connected to LPD domain could be placed in 0x8000_0000-0x9FFF_FFFF address space. But conflict is not allowed. + - As the interrupt controller is connected with **M_AXI_HPM0_LPD** domain, we need check LPD domain supported address space. Please check the [ZYNQMP Technical Reference Manual](https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/PL-AXI-Interface). You could find following address range. That means the IP connected to LPD domain could be placed in 0x8000_0000-0x9FFF_FFFF address space. But conflict is not allowed. ![Platform Setup - AXI Ports](images/LPD.PNG) diff --git a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/README.md b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/README.md index a7fcf43dd8..b495db0716 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/README.md +++ b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/README.md @@ -1,4 +1,4 @@ - +

Vitis™ Platform Creation Tutorials

See Vitis™ Development Environment on xilinx.com
 @@ -70,9 +70,9 @@ The following sections will introduce the platform creation steps. Each section ## References -- [UG1393: Vitis Acceleration Flow User Guide](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration) - - [Platform Creation General Rules](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Creating-Embedded-Platforms-in-Vitis) - - [Setting up the Vitis environment](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Setting-Up-the-Environment-to-Run-the-Vitis-Software-Platform) +- [UG1393: Vitis Acceleration Flow User Guide](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration) + - [Platform Creation General Rules](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Creating-Embedded-Platforms-in-Vitis) + - [Setting up the Vitis environment](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Setting-Up-the-Environment-to-Run-the-Vitis-Software-Platform) - Platform Examples - [zcu102](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.2/Xilinx_Official_Platforms/xilinx_zcu102_base) and [zcu104](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.2/Xilinx_Official_Platforms/xilinx_zcu104_base) base platform source code in [Vitis Embedded Platform Source Github Repository](https://github.com/Xilinx/Vitis_Embedded_Platform_Source) - [Vitis AI Github Repository](https://github.com/Xilinx/Vitis-AI) diff --git a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step1.md b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step1.md index 7a8dd5b7ac..d2c30b1e9b 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step1.md +++ b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step1.md @@ -1,4 +1,4 @@ - +

Vitis™ Platform Creation Tutorials

See Vitis™ Development Environment on xilinx.com
 @@ -256,7 +256,7 @@ When a component comes with multiple types of simulation models, selecting a Sys Next, we will use the example of modifying the interrupt controller IP address to illustrate how to modify the IP address in the address editor. - - As the interrupt controller is connected with **M_AXI_HPM0_LPD** domain, we need check LPD domain supported address space. Please check the [ZYNQMP Technical Reference Manual](https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PL-AXI-Interface). You could find following address range. That means the IP connected to LPD domain could be placed in 0x8000_0000-0x9FFF_FFFF address space. But conflict is not allowed. + - As the interrupt controller is connected with **M_AXI_HPM0_LPD** domain, we need check LPD domain supported address space. Please check the [ZYNQMP Technical Reference Manual](https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/PL-AXI-Interface). You could find following address range. That means the IP connected to LPD domain could be placed in 0x8000_0000-0x9FFF_FFFF address space. But conflict is not allowed. ![Platform Setup - AXI Ports](images/LPD.PNG) diff --git a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md index 18f4ffc7b9..bcebd83087 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md +++ b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md @@ -1,4 +1,4 @@ - +

Vitis Platform Creation Tutorials

See AMD Vitis™ Development Environment on xilinx.com
 @@ -10,7 +10,7 @@ ***Version: 2024.1*** -In this module, we treat the VCK190 board as if it were a custom solution tailored to our customer's specific needs. Our approach involves leveraging the AMD Versal™ Adaptive SoC Extensible Part Support Example Design and harnessing the power of a pre-built Linux common image, along with the createdts command, to generate essential software components. These components are then used to construct a dedicated embedded Versal acceleration platform designed exclusively for our customer's board. As the final step, you will run several applications to test this platform. If you merely create a platform to validate your kernels, then the [Vitis Platform Quick Start](https://docs.xilinx.com/r/en-US/Vitis-Tutorials-Getting-Started/Vitis-Platform) would be a quick choice for you. +In this module, we treat the VCK190 board as if it were a custom solution tailored to our customer's specific needs. Our approach involves leveraging the AMD Versal™ Adaptive SoC Extensible Part Support Example Design and harnessing the power of a pre-built Linux common image, along with the createdts command, to generate essential software components. These components are then used to construct a dedicated embedded Versal acceleration platform designed exclusively for our customer's board. As the final step, you will run several applications to test this platform. If you merely create a platform to validate your kernels, then the [Vitis Platform Quick Start](https://docs.amd.com/r/en-US/Vitis-Tutorials-Getting-Started/Vitis-Platform) would be a quick choice for you. For your reference, the overall structure of this example system closely resembles the following: @@ -25,7 +25,7 @@ In a general Vitis acceleration platform design, the Vitis platform and applicat 4. Create applications in Vitis against the platform. Vitis generates a host application, xclbin, and `sd_card.img`. 5. Write `sd_card.img` to a SD card or update host application and xclbin to an existing SD card. -In this module, you will utilize the Versal Extensible Part Support Design (CED) to create a hardware design. In contrast to the Versal Extensible Design, which is used in [Vitis Platform Quick Start](https://docs.xilinx.com/r/en-US/Vitis-Tutorials-Getting-Started/Vitis-Platform), the part support design takes a slightly different approach. Specifically, it empowers you to handle board-level configurations independently. This includes configuring processing system (PS) side peripherals and fine-tuning parameters related to double data rate (DDR) as needed. This flexibility ensures that you have full control over the configuration process to meet the unique requirements of your application. +In this module, you will utilize the Versal Extensible Part Support Design (CED) to create a hardware design. In contrast to the Versal Extensible Design, which is used in [Vitis Platform Quick Start](https://docs.amd.com/r/en-US/Vitis-Tutorials-Getting-Started/Vitis-Platform), the part support design takes a slightly different approach. Specifically, it empowers you to handle board-level configurations independently. This includes configuring processing system (PS) side peripherals and fine-tuning parameters related to double data rate (DDR) as needed. This flexibility ensures that you have full control over the configuration process to meet the unique requirements of your application. To prepare the software components, you will utilize common image released by AMD and `createdts` command to generate the device tree file. After the whole software and hardware components are ready, you will package the platform. @@ -46,9 +46,9 @@ Navigate through these steps with the following table of contents links. ## Reference -- [UG1393: Vitis Acceleration Flow User Guide](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration) +- [UG1393: Vitis Acceleration Flow User Guide](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration) - [Vitis Embedded Platform Source Github Repository](https://github.com/Xilinx/Vitis_Embedded_Platform_Source) -- [Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)](https://docs.xilinx.com/r/en-US/pg313-network-on-chip) +- [Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)](https://docs.amd.com/r/en-US/pg313-network-on-chip) ## Changelog diff --git a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step1.md b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step1.md index 2c75f8f2b9..2d1575db9a 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step1.md +++ b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step1.md @@ -1,4 +1,4 @@ - +

Vitis™ Platform Creation Tutorials

See Vitis™ Development Environment on xilinx.com
 @@ -157,7 +157,7 @@ Now you have completed the hardware design. In the coming steps, you will review Next, we will use the example of modifying the interrupt controller IP address to illustrate how to modify the IP address in the address editor. - - As the interrupt controller is connected with **M_AXI_FPD** domain, we need check FPD domain supported address space. Please check the [Versal Technical Reference Manual](https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/High-level-Address-Map). You could find following address range. That means the IP connected to FPD domain could be placed in 0xA400_0000-0xAFFF_FFFF or 0xB000_0000-0xBFFF_FFFF address space. But conflict is not allowed. + - As the interrupt controller is connected with **M_AXI_FPD** domain, we need check FPD domain supported address space. Please check the [Versal Technical Reference Manual](https://docs.amd.com/r/en-US/am011-versal-acap-trm/High-level-Address-Map). You could find following address range. That means the IP connected to FPD domain could be placed in 0xA400_0000-0xAFFF_FFFF or 0xB000_0000-0xBFFF_FFFF address space. But conflict is not allowed. ![Platform Setup - AXI Ports](images/step1/FPD.PNG) diff --git a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/README.md b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/README.md index c7678da427..8bfd54f3cd 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/README.md +++ b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/README.md @@ -44,7 +44,7 @@ This tutorial design uses VCK190 production board for demonstration. The methodo This design requires a Linux host machine with Internet access. The Linux OS needs to support the Vitis software and PetaLinux. -This tutorial assumes that you are familiar with Vitis platform creation flow. If not, refer to VCK190 Platform Creation Tutorial and *Vitis Acceleration Flow User Guide* [(UG1393)](https://docs.xilinx.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1393-vitis-application-acceleration) for more information. +This tutorial assumes that you are familiar with Vitis platform creation flow. If not, refer to VCK190 Platform Creation Tutorial and *Vitis Acceleration Flow User Guide* [(UG1393)](https://docs.amd.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1393-vitis-application-acceleration) for more information. ## What's Next @@ -52,9 +52,9 @@ Start with [Step 1](./step1.md). ## Reference -- *Vitis Acceleration Flow User Guide* [(UG1393)](https://docs.xilinx.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1393-vitis-application-acceleration) +- *Vitis Acceleration Flow User Guide* [(UG1393)](https://docs.amd.com/access/sources/dita/map?isLatest=true&ft:locale=en-US&url=ug1393-vitis-application-acceleration) - - [Creating Embedded Platforms in Vitis](https://docs.xilinx.com/access/sources/dita/topic?isLatest=true&ft:locale=en-US&url=ug1393-vitis-application-acceleration&resourceid=rjs1596051748503.html) + - [Creating Embedded Platforms in Vitis](https://docs.amd.com/access/sources/dita/topic?isLatest=true&ft:locale=en-US&url=ug1393-vitis-application-acceleration&resourceid=rjs1596051748503.html) - [Vitis Embedded Platform Source Github Repository](https://github.com/Xilinx/Vitis_Embedded_Platform_Source) diff --git a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step1.md b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step1.md index 635a8414f3..b62b5c80f0 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step1.md +++ b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step1.md @@ -1,4 +1,4 @@ - +

Vitis Platform Creation Tutorials

See AMD Vitis™ Development Environment on xilinx.com
 @@ -12,7 +12,7 @@ This hardware design illustrates how to create a DFX hardware platform. You will The major differences between the AMD Vitis™ DFX platform and flat Vitis Platform is the AMD Vivado™ design. It needs to define the Block Design Container (BDC) for reconfigurable partition. BDC defines the dynamic region, or Reconfigurable Partition (RP). -Versal devices support partial reconfiguration for almost all component types. Refer to the *Vivado Design Suite User Guide: Dynamic Function eXchange* [(UG909)](https://docs.xilinx.com/r/en-US/ug909-vivado-partial-reconfiguration/Design-Elements-Inside-Reconfigurable-Modules?tocId=zNU4eeS04V2g~W3rO2mHgA) for more details about the supported element types. +Versal devices support partial reconfiguration for almost all component types. Refer to the *Vivado Design Suite User Guide: Dynamic Function eXchange* [(UG909)](https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/Design-Elements-Inside-Reconfigurable-Modules?tocId=zNU4eeS04V2g~W3rO2mHgA) for more details about the supported element types. Here are some common practices for partitioning the IPs in Vitis platform designs. @@ -149,7 +149,7 @@ The Clock Wizard in static region is required so that the device tree generator Next, we will use the example of modifying the interrupt controller IP address to illustrate how to modify the IP address in the address editor. - - As the interrupt controller is connected with **M_AXI_FPD** domain, we need check FPD domain supported address space. Please check the [Versal Technical Reference Manual](https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/High-level-Address-Map). You could find following address range. That means the IP connected to FPD domain could be placed in 0xA400_0000-0xAFFF_FFFF or 0xB000_0000-0xBFFF_FFFF address space. But conflict is not allowed. + - As the interrupt controller is connected with **M_AXI_FPD** domain, we need check FPD domain supported address space. Please check the [Versal Technical Reference Manual](https://docs.amd.com/r/en-US/am011-versal-acap-trm/High-level-Address-Map). You could find following address range. That means the IP connected to FPD domain could be placed in 0xA400_0000-0xAFFF_FFFF or 0xB000_0000-0xBFFF_FFFF address space. But conflict is not allowed. ![Platform Setup - AXI Ports](images/step1/FPD.PNG) @@ -246,8 +246,8 @@ You have completed the Hardware platform creation flow. Next go to [step 2](./st ## References -- Turn a Block Design Container into a Reconfigurable Partition in *Vivado Design Suite User Guide: Dynamic Function eXchange* [(UG909)](https://docs.xilinx.com/r/en-US/ug909-vivado-partial-reconfiguration/Turn-a-Block-Design-Container-into-a-Reconfigurable-Partition) -- Create a Floorplan for the Reconfigurable Region in *Vivado Design Suite User Guide: Dynamic Function eXchange* [(UG909)](https://docs.xilinx.com/r/en-US/ug909-vivado-partial-reconfiguration/Create-a-Floorplan-for-the-Reconfigurable-Region) +- Turn a Block Design Container into a Reconfigurable Partition in *Vivado Design Suite User Guide: Dynamic Function eXchange* [(UG909)](https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/Turn-a-Block-Design-Container-into-a-Reconfigurable-Partition) +- Create a Floorplan for the Reconfigurable Region in *Vivado Design Suite User Guide: Dynamic Function eXchange* [(UG909)](https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/Create-a-Floorplan-for-the-Reconfigurable-Region)

Copyright © 2020–2024 Advanced Micro Devices, Inc

diff --git a/Vitis_Platform_Creation/Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md b/Vitis_Platform_Creation/Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md index 9369ebe031..66ab7317bc 100644 --- a/Vitis_Platform_Creation/Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md +++ b/Vitis_Platform_Creation/Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md @@ -1,4 +1,4 @@ - +
@@ -15,7 +15,7 @@ ## Introduction -The Vitis Export to Vivado enables bidirectional hardware hand-offs between the Vitis tools and the Vivado Design Suite to improve developer productivity in vivado. Hardware design development which includes synthesis, implementation, and timing closure can be done in Vivado Design Suite and Vitis tool can be used to do the software development, such as AI Engine (AIE) development, programmable logic (PL) kernels development and host application. This flow supports hardware emulation and testing the design on hardware. Refer UG1393 https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Export-to-Vivado-Flow for more details. +The Vitis Export to Vivado enables bidirectional hardware hand-offs between the Vitis tools and the Vivado Design Suite to improve developer productivity in vivado. Hardware design development which includes synthesis, implementation, and timing closure can be done in Vivado Design Suite and Vitis tool can be used to do the software development, such as AI Engine (AIE) development, programmable logic (PL) kernels development and host application. This flow supports hardware emulation and testing the design on hardware. Refer UG1393 https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Export-to-Vivado-Flow for more details. **IMPORTANT:** Before beginning the tutorial, make sure you have installed the Vitis 2023.2 and Vivado 2023.2 software. @@ -300,7 +300,7 @@ Here, it can be seen that the open ports in step 1.2.8 are connected using the v #### Step 4: Changes in the Vivado design after the VMA import -Developer can make the Vivado design changes in the ext_bdc_vma.bd after importing VMA except inside the hierarchy (VitisRegion.v). You can view connnection between HLS kernels to AIE inside the VitisRegion hierarchy. Refer to [UG1393]() to understand the design guidelines and limitations under the section "Vitis Export Flow Guidelines and Limitations". +Developer can make the Vivado design changes in the ext_bdc_vma.bd after importing VMA except inside the hierarchy (VitisRegion.v). You can view connnection between HLS kernels to AIE inside the VitisRegion hierarchy. Refer to [UG1393]() to understand the design guidelines and limitations under the section "Vitis Export Flow Guidelines and Limitations". **NOTE:** Any changes related to VitisRegion hierarchy in ext_bdc_vma.bd can only be done through Vitis. It is read-only in Vivado. @@ -434,7 +434,7 @@ v++ -p -t hw -f ./hw/build/my_project/vck190_prj_fixed_hw.xsa \ --package.dtb ../boot/system.dtb \ -o vck190_vitis_design_hw.xclbin ``` -To run the design on hardware, refer to the Building and Packaging section in [UG1393](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Packaging-Images). +To run the design on hardware, refer to the Building and Packaging section in [UG1393](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Packaging-Images). Use the make command to generate the xcilbin using the v++ package command for HW Emulation flow: `make package TARGET=hw_emu` @@ -478,7 +478,7 @@ In this tutorial, you learned the following after completing the tutorial: 4. Import the VMA into the Vivado and progress the platform development in the Vivado. 5. Generate the `fixed.xsa` file from the Vivado to support hardware and hardware emulation flow. -To read more about the flow, refer to [UG1393](https://docs.xilinx.com/search/all?query=Vitis+Unified+Software+Platform+Documentation%253A+Application+Acceleration+Development+(UG1393)&content-lang=en-US) (Chapter 19: Managing Vivado Synthesis, Implementation, and Timing Closure). +To read more about the flow, refer to [UG1393](https://docs.amd.com/search/all?query=Vitis+Unified+Software+Platform+Documentation%253A+Application+Acceleration+Development+(UG1393)&content-lang=en-US) (Chapter 19: Managing Vivado Synthesis, Implementation, and Timing Closure). ## Support diff --git a/Vitis_Platform_Creation/Vitis_Platform_Creation.rst b/Vitis_Platform_Creation/Vitis_Platform_Creation.rst index e588abce48..0d89fceea3 100644 --- a/Vitis_Platform_Creation/Vitis_Platform_Creation.rst +++ b/Vitis_Platform_Creation/Vitis_Platform_Creation.rst @@ -1,4 +1,4 @@ -############################################################################## +############################################################################## AMD Vitis Platform Creation Tutorials ############################################################################## @@ -21,7 +21,7 @@ Briefly speaking, a platform is a package that contains the HPFM (``.xsa``) file Platform Creation Example Quick Access ================================================================================== -* For a first experience of platforms, refer to `Vitis Platform Quick Start `_ +* For a first experience of platforms, refer to `Vitis Platform Quick Start `_ * For **ZYNQMP** device family, refer to :doc:`ZCU104 platform tutorial <./docs/Design_Tutorials/02-Edge-AI-ZCU104/README>` * For **Versal** device family, refer to :doc:`VCK190 platform tutorial <./docs/Design_Tutorials/03_Edge_VCK190/README>` * For **:term:`DFX`** platform, refer to :doc:`DFX platform tutorial <./docs/Design_Tutorials/04_Edge_VCK190_DFX/README>` @@ -66,7 +66,7 @@ Design Tutorials - IDE Flow - Design Target - * - `Vitis Platform Quick Start `_ + * - `Vitis Platform Quick Start `_ - Versal AI Core - VCK190 - Flat diff --git a/docs-jp/README.md b/docs-jp/README.md index fd676f7bed..20268e73d8 100644 --- a/docs-jp/README.md +++ b/docs-jp/README.md @@ -1,4 +1,4 @@ -

English | 日本語

+

English | 日本語

Vitis™ Platform Creation Tutorials

Vitis™ チュートリアル

@@ -8,7 +8,7 @@ 日本語版の Vitis チュートリアルは、次のサイトで提供されています。 -
https://docs.xilinx.com/v/u/ja-JP/UG1605-vitis-tutorials

+
https://docs.amd.com/v/u/ja-JP/UG1605-vitis-tutorials

内容に相違が生じる場合には原文を優先します。英語版の更新に対応していないことがありますので、日本語版は参考用としてご使用の上、最新情報につきましては、必ず最新英語版 (https://github.com/Xilinx/Vitis-Tutorials) をご参照ください。