TDL：2023.1 rebranding and editorial changes

Hardware_Acceleration/Design_Tutorials/01-convolution-tutorial/README.md

@@ -6,27 +6,26 @@
  </tr>
 </table>
 
-
 # Accelerating Video Convolution Filtering Application
 
 ***Version: Vitis 2023.1***
 
-This tutorial introduces you to a compute-intensive application that is accelerated using the Xilinx Alveo Data Center accelerator card. It goes through the design of a specific kernel that runs on the FPGA and briefly discusses optimization of the host-side application for performance. The kernel is designed to maximize throughput, and the host application is optimized to transfer data in an effective manner that moves in-between the host and FPGA card. The host application essentially eliminates the data movement latency by overlapping data transfers for multiple kernel calls. Another essential purpose of this tutorial is to show **_how one can easily estimate the performance of hardware kernels that can be built using Vitis HLS and how accurate and close these estimates are to actual hardware performance_**
+This tutorial introduces you to a compute-intensive application that is accelerated using the AMD Alveo™ Data Center accelerator card. It goes through the design of a specific kernel that runs on the field programmable gate array (FPGA) and briefly discusses optimization of the host-side application for performance. The kernel is designed to maximize throughput, and the host application is optimized to transfer data in an effective manner that moves in-between the host and FPGA card. The host application essentially eliminates the data movement latency by overlapping data transfers for multiple kernel calls. Another essential purpose of this tutorial is to show **how one can easily estimate the performance of hardware kernels that can be built using Vitis HLS and how accurate and close these estimates are to actual hardware performance**.
 
 ## Introduction to Acceleration
 
-The first lab is designed to let you quickly experience the acceleration performance that can be achieved by porting the video filter to Xilinx's Alveo accelerator card. The Alveo series cards are designed for accelerating data center applications. However, this tutorial can be adapted to other accelerator cards with some simple changes.
+The first lab is designed to let you quickly experience the acceleration performance that can be achieved by porting the video filter to AMD's Alveo accelerator card. The Alveo series cards are designed for accelerating data center applications. However, this tutorial can be adapted to other accelerator cards with some simple changes.
 
  The steps to be carried out for this first lab include:
 
 - Setting up the Vitis application acceleration development flow
 - Running the hardware optimized accelerator and comparing its performance with a baseline of the application
 
-This lab demonstrates the significant performance gain that can be achieved as compared to CPU performance. Whereas the next labs in this tutorial will illustrate and guide how such performance can be achieved using different optimizations and design techniques for 2D convolution kernels and the host side application.
+This lab demonstrates the significant performance gain that can be achieved as compared to the processor performance. The next labs in this tutorial will illustrate and guide how such performance can be achieved using different optimizations and design techniques for 2D convolution kernels and the host side application.
 
 ### Cloning the GitHub Repository and Setting Up the Vitis Tool
 
-To run this tutorial you will need to clone a git repo and also download and extract some compressed files, please follow the instruction given below:
+To run this tutorial, you will need to clone a git repo and also download and extract some compressed files. Use the following instructions:
 
 #### Clone Git Repo
 
@@ -38,19 +37,19 @@ git clone https://github.com/Xilinx/Vitis-Tutorials.git
 
 #### Copy and Extract Large Files
 
-Copy and extract large files in convolution tutorial directory as follows:
+Copy and extract large files in the convolution tutorial directory as follows:
 
 ```bash
 cd /VITIS_TUTORIAL_REPO_PATH/Hardware_Acceleration/Design_Tutorials/01-convolution-tutorial
 wget https://www.xilinx.com/bin/public/openDownload?filename=conv_tutorial_files.tar.gz -O conv_tutorial_files.tar.gz
 tar -xvzf  conv_tutorial_files.tar.gz
 ```
 
-**NOTE** : VITIS_TUTORIAL_REPO_PATH is the local directory path where git repo is cloned. 
+>**NOTE:** VITIS_TUTORIAL_REPO_PATH is the local directory path where the git repo is cloned.
 
 #### Setting Up the Vitis Tool
 
-Setup the application build and runtime environment using the following commands as per your local installation:
+Set up the application build and runtime environment using the following commands as per your local installation:
 
 ```bash
 source <XILINX_VITIS_INSTALL_PATH>/settings64.sh
@@ -59,15 +58,15 @@ source <XRT_INSTALL_PATH>/setup.sh
 
 ### Baseline the Application Performance
 
-The software application processes High Definition(HD) video frames/images with 1920x1080 resolution. It performs convolution on a set of images and prints the summary of performance results. It is used for measuring baseline software performance. Please the set the environment variable that points to tutorial direction relative to repo path as follow:
+The software application processes high definition (HD) video frames/images with 1920x1080 resolution. It performs convolution on a set of images and prints the summary of performance results. It is used for measuring baseline software performance. Set the environment variable that points to tutorial direction relative to the repo path as follows:
 
 ```bash
 export CONV_TUTORIAL_DIR=/VITIS_TUTORIAL_REPO_PATH/Hardware_Acceleration/Design_Tutorials/01-convolution-tutorial
 ```
 
-where **VITIS_TUTORIAL_REPO_PATH** is the local path where git repo is placed by the user after cloning.
+where **VITIS_TUTORIAL_REPO_PATH** is the local path where the git repo is placed by the user after cloning.
 
-  **NOTE**: Make sure during all of the labs in this tutorial you have set `CONV_TUTORIAL_DIR` variable appropriately 
+  >**NOTE:** Make sure during all of the labs in this tutorial you have set the `CONV_TUTORIAL_DIR` variable appropriately.
 
 Run the application to measure performance as follows:
 
@@ -76,7 +75,7 @@ cd $CONV_TUTORIAL_DIR/sw_run
 ./run.sh 
 ```
 
-Results similar to the ones shown below will be printed. Note down the CPU throughput.
+Results similar to the following will be printed. Note down the CPU throughput.
 
 ```bash
 ----------------------------------------------------------------------------
@@ -97,14 +96,14 @@ CPU  Throughput   :    12.7112 MB/s
 
 ### Launching the Host Application
 
-Now launch the application, which uses FPGA accelerated video convolution filter. The application will be run on an actual FPGA card, also called System Run.
+Now launch the application, which uses a FPGA accelerated video convolution filter. The application will be run on an actual FPGA card, also called System Run.
 
 ```bash
 cd $CONV_TUTORIAL_DIR
 make run
 ```
 
-The result summary will be similar to the one given below:
+The result summary will be similar to the following:
 
 ```bash
 ----------------------------------------------------------------------------
@@ -136,15 +135,14 @@ FPGA Speedup      :    68.1764 x
 
 ### Results
 
- From the host application console output, it is clear that the FPGA accelerated kernel can outperform CPU-only implementation by a factor of 68x. It is a large gain in terms of performance over CPU. The following labs will illustrate how this performance allows processing more than 3 HD video channels with 1080p resolution in parallel. The tutorial describes how to achieve such performance gains by building a kernel and host application written in C++.  The host application uses OpenCL APIs and Xilinx Runtime (XRT) underneath it, demonstrating how to unleash this custom-built hardware kernel's computing power effectively.
+ From the host application console output, it is clear that the FPGA accelerated kernel can outperform CPU-only implementation by a factor of 68x. It is a large gain in terms of performance over CPU. The following labs will illustrate how this performance allows processing more than three HD video channels with 1080p resolution in parallel. The tutorial describes how to achieve such performance gains by building a kernel and host application written in C++.  The host application uses OpenCL™ APIs and Xilinx Runtime (XRT) underneath it, demonstrating how to unleash this custom-built hardware kernel's computing power effectively.
 
 ---------------------------------------
 
 <p align="center"><b>
 Next Lab Module: <a href="./lab1_app_introduction_performance_estimation.md">Video Convolution Filter : Introduction and Performance Estimation</a>
  </b></p>
 
-
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