Releases: Xilinx/fpga24_routing_contest
Releases · Xilinx/fpga24_routing_contest
v1.1
Note that benchmarks.tar.gz
has changed from v1.0:
Compared to the benchmarks released in v1.0, the benchmarks in the upcoming release contain nets with alternate sources set up, where available. Alternate sources typically refer to the ability for a LUT to exit its SLICE using up to 2 pins -- for an
A6LUT
these pins areA_O
(always available) andAMUX
(available if not used for another purpose). Considering both pins, where available, can improve routability, though there are no restrictions on which of the two (or whether both) source pins are used to connect to which sink pins.
See #10 for more details.
What's Changed
- Add net_printer/README.md by @zakn-amd in #2
- Add benchmarks page by @zakn-amd in #3
- GitHub Actions to run example routers by @eddieh-xlnx in #6
- Updating FPGAIF links, team size and FAQ by @clavin-xlnx in #7
- [Doc] Explain benchmark OOC and GitHub Actions by @eddieh-xlnx in #8
- Example net_printer usage using GitHub Actions by @eddieh-xlnx in #9
- Fix typo Xmx -> Xms by @eddieh-xlnx in #14
- Add ability to execute report_route_status on remote server by @eddieh-xlnx in #16
- [Doc] Note on RWRoute memory req & VERBOSE flag by @eddieh-xlnx in #18
- Add GitHub Repo button to sidebar by @eddieh-xlnx in #17
- Makefile to download latest benchmarks.tar.gz by @eddieh-xlnx in #19
- Contest-specific DCP to FPGA Interchange Format Utility by @eddieh-xlnx in #10
Full Changelog: v1.0...v1.1
v1.0
Initial release.