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Releases: Xilinx/fpga24_routing_contest

v1.1

17 Oct 19:48
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Note that benchmarks.tar.gz has changed from v1.0:

Compared to the benchmarks released in v1.0, the benchmarks in the upcoming release contain nets with alternate sources set up, where available. Alternate sources typically refer to the ability for a LUT to exit its SLICE using up to 2 pins -- for an A6LUT these pins are A_O (always available) and AMUX (available if not used for another purpose). Considering both pins, where available, can improve routability, though there are no restrictions on which of the two (or whether both) source pins are used to connect to which sink pins.

See #10 for more details.

What's Changed

Full Changelog: v1.0...v1.1

v1.0

15 Sep 23:39
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Initial release.