From 0e2d85b261e22dd8b1933d4e1b82f6bf7499249b Mon Sep 17 00:00:00 2001 From: Krishnam Tibrewala Date: Mon, 23 Sep 2024 02:27:52 -0700 Subject: [PATCH] [AIEX] NFC: Refactor Alternate Descriptor codebase --- llvm/lib/Target/AIE/AIE2InstrInfo.cpp | 14 +++- llvm/lib/Target/AIE/AIEAlternateDescriptors.h | 74 +++++++++++++++++++ llvm/lib/Target/AIE/AIEBundle.h | 10 +-- llvm/lib/Target/AIE/AIEHazardRecognizer.cpp | 25 +++---- llvm/lib/Target/AIE/AIEHazardRecognizer.h | 14 ++-- .../Target/AIE/AIEHazardRecognizerPRAS.cpp | 3 +- llvm/lib/Target/AIE/AIEHazardRecognizerPRAS.h | 1 + .../Target/AIE/AIEInterBlockScheduling.cpp | 2 +- llvm/lib/Target/AIE/AIEInterBlockScheduling.h | 3 + llvm/lib/Target/AIE/AIEMachineScheduler.cpp | 11 ++- llvm/lib/Target/AIE/AIEMachineScheduler.h | 11 +++ .../Target/AIE/AIEScheduleDAGMITest.cpp | 5 +- llvm/unittests/Target/AIE/BundleTest.cpp | 2 +- .../Target/AIE/HazardRecognizerTest.cpp | 8 +- 14 files changed, 148 insertions(+), 35 deletions(-) create mode 100644 llvm/lib/Target/AIE/AIEAlternateDescriptors.h diff --git a/llvm/lib/Target/AIE/AIE2InstrInfo.cpp b/llvm/lib/Target/AIE/AIE2InstrInfo.cpp index ce01ab1cc887..d47f6d3fe5b1 100644 --- a/llvm/lib/Target/AIE/AIE2InstrInfo.cpp +++ b/llvm/lib/Target/AIE/AIE2InstrInfo.cpp @@ -20,6 +20,7 @@ #include "AIE2TargetMachine.h" #include "AIEHazardRecognizer.h" #include "AIEMachineFunctionInfo.h" +#include "AIEMachineScheduler.h" #include "AIETiedRegOperands.h" #include "MCTargetDesc/AIE2MCTargetDesc.h" #include "MCTargetDesc/AIEMCFormats.h" @@ -912,12 +913,23 @@ ScheduleHazardRecognizer *AIE2InstrInfo::CreateTargetPostRAHazardRecognizer( "Please use the MI scheduler instead: postmisched"); } +static AIEAlternateDescriptors &getSelectedAltDescs(const ScheduleDAGMI *DAG) { + if (DAG->hasVRegLiveness()) + return static_cast(DAG) + ->getSchedImpl() + ->getSelectedAltDescs(); + return static_cast(DAG) + ->getSchedImpl() + ->getSelectedAltDescs(); +} + ScheduleHazardRecognizer * AIE2InstrInfo::CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const { // AIE has a fully exposed pipeline, resource and format conflicts must be // exactly modelled. - return new AIEHazardRecognizer(this, II, /*IsPreRA=*/DAG->hasVRegLiveness()); + return new AIEHazardRecognizer(this, II, getSelectedAltDescs(DAG), + /*IsPreRA=*/DAG->hasVRegLiveness()); } /// insertNoop - Insert a noop into the instruction stream at the specified diff --git a/llvm/lib/Target/AIE/AIEAlternateDescriptors.h b/llvm/lib/Target/AIE/AIEAlternateDescriptors.h new file mode 100644 index 000000000000..01673a348efd --- /dev/null +++ b/llvm/lib/Target/AIE/AIEAlternateDescriptors.h @@ -0,0 +1,74 @@ +//== AIEAlternateDescriptors.h - Define Alternate descriptor Class *-C++-*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates +// +//===----------------------------------------------------------------------===// +// +// This file declares the AIEngine Alternate instruction descriptor class +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_SUPPORT_AIEALTERNATEDESCRIPTORS_H +#define LLVM_SUPPORT_AIEALTERNATEDESCRIPTORS_H + +#include "AIEBaseSubtarget.h" +#include "MCTargetDesc/AIEMCFormats.h" + +#include + +namespace llvm { + +using MIAltDescsMap = std::unordered_map; + +class AIEAlternateDescriptors { + MIAltDescsMap AlternateDescs; + +public: + AIEAlternateDescriptors() = default; + ~AIEAlternateDescriptors() = default; + + // Construct an alternate descriptor with the given alternate descriptors. + AIEAlternateDescriptors(const MIAltDescsMap &AltDescs) + : AlternateDescs(AltDescs) {} + + // Set the alternate descriptor for the given multi-opcode instruction. + void setAlternateDescriptor(MachineInstr *MI, const unsigned AltInstOpcode) { + const AIEBaseSubtarget &STI = AIEBaseSubtarget::get(*MI->getMF()); + const AIEBaseInstrInfo *TII = STI.getInstrInfo(); + + AlternateDescs[MI] = &TII->get(AltInstOpcode); + } + + // Return the alternate descriptor for the given multi-opcode instruction. + std::optional + getSelectedDescriptor(MachineInstr *MI) const { + if (auto It = AlternateDescs.find(MI); It != AlternateDescs.end()) + return It->second; + return std::nullopt; + } + + const MCInstrDesc *getDesc(MachineInstr *MI) const { + return getSelectedDescriptor(MI).value_or(&MI->getDesc()); + } + + // Return the alternate opcode for the given multi-opcode instruction. + std::optional getSelectedOpcode(MachineInstr *MI) const { + if (auto It = AlternateDescs.find(MI); It != AlternateDescs.end()) + return It->second->getOpcode(); + return std::nullopt; + } + + unsigned getOpcode(MachineInstr *MI) const { + return getSelectedOpcode(MI).value_or(MI->getDesc().getOpcode()); + } + + void clear() { AlternateDescs.clear(); } +}; + +} // end namespace llvm + +#endif // LLVM_SUPPORT_AIEALTERNATEDESCRIPTOR_H diff --git a/llvm/lib/Target/AIE/AIEBundle.h b/llvm/lib/Target/AIE/AIEBundle.h index c5b2c8f941d9..324c174b0c60 100644 --- a/llvm/lib/Target/AIE/AIEBundle.h +++ b/llvm/lib/Target/AIE/AIEBundle.h @@ -50,7 +50,7 @@ template class Bundle { : FormatInterface(FormatInterface) { bool ComputeSlots = (FormatInterface != nullptr); for (I *Instr : Instrs) { - add(Instr, std::nullopt, ComputeSlots); + add(Instr, Instr->getOpcode(), ComputeSlots); } } @@ -98,8 +98,7 @@ template class Bundle { /// Add an instruction to the bundle /// \param Instr Instruction to add /// \pre canAdd(Instr); - void add(I *Instr, std::optional SelectedOpcode = std::nullopt, - bool ComputeSlots = true) { + void add(I *Instr, unsigned OpCode, bool ComputeSlots = true) { if (isNoHazardMetaInstruction(Instr->getOpcode())) { MetaInstrs.push_back(Instr); return; @@ -113,8 +112,7 @@ template class Bundle { if (!ComputeSlots) return; - MCSlotKind FinalSlot = FormatInterface->getSlotKind( - SelectedOpcode ? *SelectedOpcode : Instr->getOpcode()); + MCSlotKind FinalSlot = FormatInterface->getSlotKind(OpCode); if (FinalSlot == MCSlotKind()) { assert(Instrs.size() == 1 && "Tried to add an unknown slot instruction in a valid Bundle"); @@ -127,6 +125,8 @@ template class Bundle { OccupiedSlots |= NewSlots; } + void add(I *Instr) { add(Instr, Instr->getOpcode()); } + /// return the minimum size valid format for this bundle, if any const VLIWFormat *getFormatOrNull(unsigned Size = 0) const { assert(!isStandalone()); diff --git a/llvm/lib/Target/AIE/AIEHazardRecognizer.cpp b/llvm/lib/Target/AIE/AIEHazardRecognizer.cpp index 942ed9dd782c..5eb8dfa3a943 100644 --- a/llvm/lib/Target/AIE/AIEHazardRecognizer.cpp +++ b/llvm/lib/Target/AIE/AIEHazardRecognizer.cpp @@ -183,9 +183,10 @@ static cl::opt int AIEHazardRecognizer::NumInstrsScheduled = 0; AIEHazardRecognizer::AIEHazardRecognizer( - const AIEBaseInstrInfo *TII, const InstrItineraryData *II, bool IsPreRA, + const AIEBaseInstrInfo *TII, const InstrItineraryData *II, + AIEAlternateDescriptors &SelectedAlternateDescs, bool IsPreRA, std::optional ScoreboardDepth) - : TII(TII), ItinData(II) { + : TII(TII), ItinData(II), SelectedAltDescs(SelectedAlternateDescs) { int Depth = 0; if (ScoreboardDepth.has_value()) { @@ -213,11 +214,12 @@ AIEHazardRecognizer::AIEHazardRecognizer( } } -AIEHazardRecognizer::AIEHazardRecognizer(const TargetSubtargetInfo &Subtarget, - bool IsPreRA) +AIEHazardRecognizer::AIEHazardRecognizer( + const TargetSubtargetInfo &Subtarget, + AIEAlternateDescriptors &SelectedAlternateDescs, bool IsPreRA) : AIEHazardRecognizer( static_cast(Subtarget.getInstrInfo()), - Subtarget.getInstrItineraryData(), IsPreRA) {} + Subtarget.getInstrItineraryData(), SelectedAlternateDescs, IsPreRA) {} namespace llvm { void applyFormatOrdering(AIE::MachineBundle &Bundle, const VLIWFormat &Format, @@ -292,7 +294,7 @@ void AIEHazardRecognizer::Reset() { LLVM_DEBUG(dbgs() << "Reset hazard recognizer\n"); ReservedCycles = 0; Scoreboard.clear(); - SelectedAltOpcodes.clear(); + SelectedAltDescs.clear(); } ScheduleHazardRecognizer::HazardType @@ -324,7 +326,7 @@ AIEHazardRecognizer::getHazardType(SUnit *SU, int DeltaCycles) { // Check if there is NoHazard, If there is a Hazard or NoopHazard check // for the next possible Opcode. if (Haz == NoHazard) { - SelectedAltOpcodes[MI] = AltInstOpcode; + SelectedAltDescs.setAlternateDescriptor(MI, AltInstOpcode); return NoHazard; } } @@ -385,7 +387,7 @@ void AIEHazardRecognizer::EmitInstruction(SUnit *SU, int DeltaCycles) { // If the instruction has multiple options, find the opcode that was selected // and use the latter to update the scoreboard. - unsigned SelectedOpcode = getSelectedAltOpcode(MI).value_or(MI->getOpcode()); + unsigned SelectedOpcode = SelectedAltDescs.getOpcode(MI); if (!AIE::MachineBundle::isNoHazardMetaInstruction(SelectedOpcode)) emitInScoreboard(TII->get(SelectedOpcode), getMemoryBanks(MI), MI->operands(), MI->getMF()->getRegInfo(), DeltaCycles); @@ -616,13 +618,6 @@ unsigned AIEHazardRecognizer::computeScoreboardDepth() const { return std::max(Depth, UserScoreboardDepth.getValue()); } -std::optional -AIEHazardRecognizer::getSelectedAltOpcode(MachineInstr *MI) const { - if (auto It = SelectedAltOpcodes.find(MI); It != SelectedAltOpcodes.end()) - return It->second; - return std::nullopt; -} - MemoryBankBits AIEHazardRecognizer::getMemoryBanks(const MachineInstr *MI) const { if (!(MI->mayLoad() || MI->mayStore())) diff --git a/llvm/lib/Target/AIE/AIEHazardRecognizer.h b/llvm/lib/Target/AIE/AIEHazardRecognizer.h index c97382f493a2..2e712e7c5ae8 100644 --- a/llvm/lib/Target/AIE/AIEHazardRecognizer.h +++ b/llvm/lib/Target/AIE/AIEHazardRecognizer.h @@ -13,7 +13,7 @@ #ifndef LLVM_LIB_TARGET_AIE_AIEHAZARDRECOGNIZER_H #define LLVM_LIB_TARGET_AIE_AIEHAZARDRECOGNIZER_H -#include "AIEBaseAddrSpaceInfo.h" +#include "AIEAlternateDescriptors.h" #include "AIEBaseSubtarget.h" #include "AIEBundle.h" #include "MCTargetDesc/AIEMCFormats.h" @@ -103,9 +103,11 @@ class AIEHazardRecognizer : public ScheduleHazardRecognizer { /// scheduling model. This is mostly used for testing, for other cases we /// should trust the instruction itineraries. AIEHazardRecognizer(const AIEBaseInstrInfo *TII, const InstrItineraryData *II, + AIEAlternateDescriptors &SelectedAlternateDescs, bool IsPreRA, std::optional ScoreboardDepth = std::nullopt); AIEHazardRecognizer(const TargetSubtargetInfo &SubTarget, + AIEAlternateDescriptors &SelectedAlternateDescs, bool IsPreRA = false); ~AIEHazardRecognizer() override {} @@ -156,10 +158,6 @@ class AIEHazardRecognizer : public ScheduleHazardRecognizer { // Dump the scoreboard void dumpScoreboard() const; - /// For instructions with multiple "alternative opcodes", this will return - /// the opcode selected during scheduling. - std::optional getSelectedAltOpcode(MachineInstr *MI) const; - /// The instructions with memory bank attribute return the address space /// number MemoryBankBits getMemoryBanks(const MachineInstr *MI) const; @@ -182,6 +180,10 @@ class AIEHazardRecognizer : public ScheduleHazardRecognizer { /// For efficiency, this size is rounded up to a power of two. unsigned computeScoreboardDepth() const; + AIEAlternateDescriptors &getSelectedAltDescs() const { + return SelectedAltDescs; + } + ScheduleHazardRecognizer::HazardType getHazardType(const ResourceScoreboard &TheScoreboard, const MCInstrDesc &Desc, MemoryBankBits MemoryBanks, @@ -209,9 +211,9 @@ class AIEHazardRecognizer : public ScheduleHazardRecognizer { private: ResourceScoreboard Scoreboard; - std::map SelectedAltOpcodes; const AIEBaseInstrInfo *TII; const InstrItineraryData *ItinData; + AIEAlternateDescriptors &SelectedAltDescs; static int NumInstrsScheduled; unsigned IssueLimit = 1; unsigned ReservedCycles = 0; diff --git a/llvm/lib/Target/AIE/AIEHazardRecognizerPRAS.cpp b/llvm/lib/Target/AIE/AIEHazardRecognizerPRAS.cpp index b10a1136f8bc..521fc39dee06 100644 --- a/llvm/lib/Target/AIE/AIEHazardRecognizerPRAS.cpp +++ b/llvm/lib/Target/AIE/AIEHazardRecognizerPRAS.cpp @@ -24,7 +24,8 @@ using namespace llvm; AIEHazardRecognizerPRAS::AIEHazardRecognizerPRAS(const AIEBaseInstrInfo *TII, const InstrItineraryData *II) - : AIEHazardRecognizer(TII, II, /*IsPreRA=*/false), + : AIEHazardRecognizer(TII, II, PRASAlternateDescriptors, + /*IsPreRA=*/false), CurrentBundle(TII->getFormatInterface()) {} void AIEHazardRecognizerPRAS::StartBlock(MachineBasicBlock *MBB) {} diff --git a/llvm/lib/Target/AIE/AIEHazardRecognizerPRAS.h b/llvm/lib/Target/AIE/AIEHazardRecognizerPRAS.h index 0271bc326393..a3376d7763f9 100644 --- a/llvm/lib/Target/AIE/AIEHazardRecognizerPRAS.h +++ b/llvm/lib/Target/AIE/AIEHazardRecognizerPRAS.h @@ -47,6 +47,7 @@ class AIEHazardRecognizerPRAS : public AIEHazardRecognizer { private: std::vector Bundles; AIE::MachineBundle CurrentBundle; + AIEAlternateDescriptors PRASAlternateDescriptors; }; } // end namespace llvm diff --git a/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp b/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp index f61be9369431..be4fd26b295e 100644 --- a/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp +++ b/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp @@ -176,7 +176,7 @@ void InterBlockScheduling::enterFunction(MachineFunction *MF) { // Get ourselves a hazard recognizer const auto &Subtarget = MF->getSubtarget(); - HR = std::make_unique(Subtarget); + HR = std::make_unique(Subtarget, SelectedAltDescs); // And a native InstrInfo TII = static_cast(Subtarget.getInstrInfo()); diff --git a/llvm/lib/Target/AIE/AIEInterBlockScheduling.h b/llvm/lib/Target/AIE/AIEInterBlockScheduling.h index 19f1d3a474cf..7784a2256623 100644 --- a/llvm/lib/Target/AIE/AIEInterBlockScheduling.h +++ b/llvm/lib/Target/AIE/AIEInterBlockScheduling.h @@ -297,6 +297,7 @@ class InterBlockScheduling { // A hazard recognizer to interpret itineraries std::unique_ptr HR; + AIEAlternateDescriptors SelectedAltDescs; std::map Blocks; std::vector MBBSequence; unsigned NextInOrder = 0; @@ -393,6 +394,8 @@ class InterBlockScheduling { void emitInterBlockBottom(const BlockState &BS) const; bool tryPipeline(ScheduleDAGMI &DAG, MachineBasicBlock *BB); + + AIEAlternateDescriptors &getSelectedAltDescs() { return SelectedAltDescs; } }; } // end namespace llvm::AIE diff --git a/llvm/lib/Target/AIE/AIEMachineScheduler.cpp b/llvm/lib/Target/AIE/AIEMachineScheduler.cpp index 37351196d275..cda5c78c5c98 100644 --- a/llvm/lib/Target/AIE/AIEMachineScheduler.cpp +++ b/llvm/lib/Target/AIE/AIEMachineScheduler.cpp @@ -166,7 +166,8 @@ llvm::AIE::computeAndFinalizeBundles(SchedBoundary &Zone) { bumpCycleForBundles(EmitCycle, Bundles, CurrBundle); LLVM_DEBUG(dbgs() << " Add to CurrBundle: " << MI); - CurrBundle.add(&MI, HazardRec.getSelectedAltOpcode(&MI), ComputeSlots); + CurrBundle.add(&MI, HazardRec.getSelectedAltDescs().getOpcode(&MI), + ComputeSlots); } }; @@ -594,6 +595,7 @@ void AIEPostRASchedStrategy::leaveRegion(const SUnit &ExitSU) { return; } materializeMultiOpcodeInstrs(); + InterBlock.getSelectedAltDescs().clear(); if (IsBottomRegion) { // This is the earliest point where we can destroy the recorded // schedule in iterative scheduling. enterMBB and enterRegion are too early, @@ -625,7 +627,7 @@ void AIEPostRASchedStrategy::materializeMultiOpcodeInstrs() { const AIEHazardRecognizer &HazardRec) { // Materialize instructions with multiple opcode options if (std::optional AltOpcode = - HazardRec.getSelectedAltOpcode(&MI)) { + HazardRec.getSelectedAltDescs().getSelectedOpcode(&MI)) { MI.setDesc(TII->get(*AltOpcode)); } }; @@ -831,6 +833,7 @@ void AIEPreRASchedStrategy::leaveRegion(const SUnit &ExitSU) { RegionBegin = nullptr; RegionEnd = nullptr; SUDelayerMap.clear(); + SelectedAltDescs.clear(); } PressureDiff estimatePressureDiff(const SUnit &SU, @@ -1110,6 +1113,10 @@ void AIEScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { SchedImpl->releaseBottomNode(PredSU); } +AIEPreRASchedStrategy *AIEScheduleDAGMILive::getSchedImpl() const { + return static_cast(SchedImpl.get()); +} + void AIEScheduleDAGMILive::enterRegion(MachineBasicBlock *BB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, diff --git a/llvm/lib/Target/AIE/AIEMachineScheduler.h b/llvm/lib/Target/AIE/AIEMachineScheduler.h index 683a07037668..ef8bf62b9ad7 100644 --- a/llvm/lib/Target/AIE/AIEMachineScheduler.h +++ b/llvm/lib/Target/AIE/AIEMachineScheduler.h @@ -93,6 +93,10 @@ class AIEPostRASchedStrategy : public PostGenericScheduler { const AIE::InterBlockScheduling &getInterBlock() const { return InterBlock; } AIE::InterBlockScheduling &getInterBlock() { return InterBlock; } + AIEAlternateDescriptors &getSelectedAltDescs() { + return InterBlock.getSelectedAltDescs(); + } + protected: /// Apply a set of heuristics to a new candidate for PostRA scheduling. /// @@ -166,6 +170,8 @@ class AIEPreRASchedStrategy : public GenericScheduler { bool isAvailableNode(SUnit &SU, SchedBoundary &Zone, bool VerifyReadyCycle) override; + AIEAlternateDescriptors &getSelectedAltDescs() { return SelectedAltDescs; } + protected: /// Whether \p DelayedSU can be safely delayed without forming a cycle /// of SUs delaying each other indefinitely. @@ -192,6 +198,8 @@ class AIEPreRASchedStrategy : public GenericScheduler { std::vector SUDelayerMap; std::vector PSetThresholds; + + AIEAlternateDescriptors SelectedAltDescs; }; /// An extension to ScheduleDAGMI that provides callbacks on region entry/exit @@ -230,6 +238,9 @@ class AIEScheduleDAGMILive final : public ScheduleDAGMILive { unsigned RegionInstrs) override; void exitRegion() override; + + // Give dag mutators access to the scheduler state + AIEPreRASchedStrategy *getSchedImpl() const; }; } // end namespace llvm diff --git a/llvm/unittests/Target/AIE/AIEScheduleDAGMITest.cpp b/llvm/unittests/Target/AIE/AIEScheduleDAGMITest.cpp index 77a3e98dbe74..e8dac08fbc3c 100644 --- a/llvm/unittests/Target/AIE/AIEScheduleDAGMITest.cpp +++ b/llvm/unittests/Target/AIE/AIEScheduleDAGMITest.cpp @@ -27,9 +27,12 @@ void PrintTo(const MachineBundle &B, std::ostream *OS) { namespace { class DummyAIEHazardRecognizer : public AIEHazardRecognizer { + AIEAlternateDescriptors AlternateDescriptors; + public: DummyAIEHazardRecognizer(const ScheduleDAG *DAG) - : AIEHazardRecognizer(nullptr, nullptr, DAG, /*ScoreboardDepth=*/0) {} + : AIEHazardRecognizer(nullptr, nullptr, AlternateDescriptors, DAG, + /*ScoreboardDepth=*/0) {} ~DummyAIEHazardRecognizer() override {} diff --git a/llvm/unittests/Target/AIE/BundleTest.cpp b/llvm/unittests/Target/AIE/BundleTest.cpp index e0f7ad823f71..8fe68d30a73e 100644 --- a/llvm/unittests/Target/AIE/BundleTest.cpp +++ b/llvm/unittests/Target/AIE/BundleTest.cpp @@ -241,7 +241,7 @@ TEST(Bundle, AddUnknowns) { // Test we can create a bundle of two unknown instructions // when not computing VLIW formats. B.add(Unknown); - B.add(Unknown, std::nullopt, /*ComputeSlots=*/false); + B.add(Unknown, Unknown->getOpcode(), /*ComputeSlots=*/false); EXPECT_EQ(B.size(), unsigned(2)); } diff --git a/llvm/unittests/Target/AIE/HazardRecognizerTest.cpp b/llvm/unittests/Target/AIE/HazardRecognizerTest.cpp index 4ccce99f9f50..f4b1b6d2ba8b 100644 --- a/llvm/unittests/Target/AIE/HazardRecognizerTest.cpp +++ b/llvm/unittests/Target/AIE/HazardRecognizerTest.cpp @@ -86,15 +86,19 @@ MockItineraries Itins; // Derived class to access protected methods class MockHR : public AIEHazardRecognizer { + AIEAlternateDescriptors AlternateDescriptors; ResourceScoreboard MockScoreboard; public: ~MockHR() = default; - MockHR() : AIEHazardRecognizer(&DummyInstrInfo, &Itins, /*IsPreRA=*/false) { + MockHR() + : AIEHazardRecognizer(&DummyInstrInfo, &Itins, AlternateDescriptors, + /*IsPreRA=*/false) { MockScoreboard.reset(computeScoreboardDepth()); } MockHR(const AIEBaseInstrInfo &InstrInfo) - : AIEHazardRecognizer(&InstrInfo, &Itins, /*IsPreRA=*/false) { + : AIEHazardRecognizer(&InstrInfo, &Itins, AlternateDescriptors, + /*IsPreRA=*/false) { MockScoreboard.reset(computeScoreboardDepth()); } void emit(unsigned SchedClass, int Delta, SlotBits SlotSet = 0,