[AIE2P] Add end-2-end test for i64 element vector insertions

Author: khallouh

llvm/test/CodeGen/AIE/aie2p/insert-element-64bits.ll

@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;
+; This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+;
+; (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
+; RUN: llc -mtriple=aie2p -verify-machineinstrs -o - < %s | FileCheck %s
+
+define dso_local noundef <64 x i8> @insert_element_64(<8 x i64> noundef %v, i32 noundef %idx, i64 noundef %b) local_unnamed_addr  {
+; CHECK-LABEL: insert_element_64:
+; CHECK:         .p2align 4
+; CHECK-NEXT:  // %bb.0: // %entry
+; CHECK-NEXT:    vlda bmll0, [sp, #-64]; nopb ; nops ; nopxm ; nopv
+; CHECK-NEXT:    nopx
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    mov r4, r1
+; CHECK-NEXT:    ret lr
+; CHECK-NEXT:    mov r29, r0 // Delay Slot 5
+; CHECK-NEXT:    mov r5, r2 // Delay Slot 4
+; CHECK-NEXT:    vmov x0, bmll0 // Delay Slot 3
+; CHECK-NEXT:    vinsert.64 x0, x0, r29, r5:r4 // Delay Slot 2
+; CHECK-NEXT:    nop // Delay Slot 1
+entry:
+  %vecins.i.i = insertelement <8 x i64> %v, i64 %b, i32 %idx
+  %2 = bitcast <8 x i64> %vecins.i.i to <64 x i8>
+  ret <64 x i8> %2
+}