Skip to content

Commit 2bea207

Browse files
niwinantoniwinanto
committed
[AIE2P] Spill composed vector registers to stack
Upon spilling the composed register, we might need to select the spill/reload instruction based on the register allocated by the register allocator itself.
1 parent d3d4d34 commit 2bea207

File tree

3 files changed

+63
-26
lines changed

3 files changed

+63
-26
lines changed

‎llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.cpp‎

Lines changed: 51 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -812,6 +812,8 @@ Register AIE2PInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
812812
case AIE2P::LDA_DS_SPILL:
813813
case AIE2P::VLDA_EX_SPILL:
814814
case AIE2P::VLDA_E_SPILL:
815+
case AIE2P::VLDA_512_COMPOSED_REG_SPILL:
816+
case AIE2P::VLDA_1024_COMPOSED_REG_SPILL:
815817
break;
816818
}
817819

@@ -845,6 +847,8 @@ Register AIE2PInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
845847
case AIE2P::VST_Y_SPILL:
846848
case AIE2P::VST_E_SPILL:
847849
case AIE2P::VST_EX_SPILL:
850+
case AIE2P::VST_512_COMPOSED_REG_SPILL:
851+
case AIE2P::VST_1024_COMPOSED_REG_SPILL:
848852
break;
849853
}
850854

@@ -883,6 +887,10 @@ void AIE2PInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
883887
<< "\n");
884888
if (regClassMatches(AIE2P::mSclStRegClass, RC, SrcReg)) {
885889
Opcode = AIE2P::ST_R_SPILL;
890+
} else if (&AIE2P::spill_vec1024_to_compositeRegClass == RC) {
891+
Opcode = AIE2P::VST_1024_COMPOSED_REG_SPILL;
892+
} else if (&AIE2P::spill_vec512_to_compositeRegClass == RC) {
893+
Opcode = AIE2P::VST_512_COMPOSED_REG_SPILL;
886894
} else if (regClassMatches(AIE2P::mQQssRegClass, RC, SrcReg)) {
887895
Opcode = AIE2P::ST_dmv_sts_q_spill;
888896
} else if (regClassMatches(AIE2P::mBMsRegClass, RC, SrcReg)) {
@@ -913,14 +921,6 @@ void AIE2PInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
913921
Opcode = AIE2P::VST_E_SPILL;
914922
} else if (regClassMatches(AIE2P::VEC576RegClass, RC, SrcReg)) {
915923
Opcode = AIE2P::VST_EX_SPILL;
916-
} else if (&AIE2P::spill_acc1024_to_compositeRegClass == RC) {
917-
Opcode = AIE2P::VST_CM_SPILL;
918-
} else if (&AIE2P::spill_acc512_to_compositeRegClass == RC) {
919-
Opcode = AIE2P::VST_dmx_sts_bm_spill;
920-
} else if (&AIE2P::spill_vec1024_to_compositeRegClass == RC) {
921-
Opcode = AIE2P::VST_Y_SPILL;
922-
} else if (&AIE2P::spill_vec512_to_compositeRegClass == RC) {
923-
Opcode = AIE2P::VST_dmx_sts_x_spill;
924924
} else if (regClassMatches(AIE2P::eSRegClass, RC, SrcReg) ||
925925
regClassMatches(AIE2P::spill_eS_to_eRRegClass, RC, SrcReg)) {
926926
// Can't spill these directly. Need to bounce through a GPR.
@@ -972,12 +972,17 @@ void AIE2PInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
972972
RC = constrainRegClass(MBB.getParent()->getRegInfo(), RC, DstReg);
973973
if (regClassMatches(AIE2P::mLdaSclRegClass, RC, DstReg)) {
974974
Opcode = AIE2P::LDA_R_SPILL;
975+
} else if (&AIE2P::spill_vec1024_to_compositeRegClass == RC) {
976+
Opcode = AIE2P::VLDA_1024_COMPOSED_REG_SPILL;
977+
} else if (&AIE2P::spill_vec512_to_compositeRegClass == RC) {
978+
// I->dump();
979+
Opcode = AIE2P::VLDA_512_COMPOSED_REG_SPILL;
975980
} else if (regClassMatches(AIE2P::mQQssRegClass, RC, DstReg)) {
976981
Opcode = AIE2P::LDA_dmv_lda_q_spill;
977982
} else if (regClassMatches(AIE2P::VEC256RegClass, RC, DstReg)) {
978983
Opcode = AIE2P::VLDA_dmw_lda_w_spill;
979984
} else if (regClassMatches(AIE2P::mBMsRegClass, RC, DstReg)) {
980-
I->dump();
985+
// I->dump();
981986
Opcode = AIE2P::VLDA_dmx_lda_bm_spill;
982987
} else if (regClassMatches(AIE2P::mFifoHLRegRegClass, RC, DstReg)) {
983988
Opcode = AIE2P::VLDA_dmx_lda_fifohl_spill;
@@ -986,7 +991,7 @@ void AIE2PInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
986991
} else if (regClassMatches(AIE2P::ACC2048RegClass, RC, DstReg)) {
987992
Opcode = AIE2P::VLDA_DM_SPILL;
988993
} else if (regClassMatches(AIE2P::ACC1024RegClass, RC, DstReg)) {
989-
I->dump();
994+
// I->dump();
990995
Opcode = AIE2P::VLDA_CM_SPILL;
991996
} else if (regClassMatches(AIE2P::FIFO1024RegClass, RC, DstReg)) {
992997
Opcode = AIE2P::VLDA_FIFO_SPILL;
@@ -1004,15 +1009,6 @@ void AIE2PInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
10041009
Opcode = AIE2P::VLDA_E_SPILL;
10051010
} else if (regClassMatches(AIE2P::VEC576RegClass, RC, DstReg)) {
10061011
Opcode = AIE2P::VLDA_EX_SPILL;
1007-
} else if (&AIE2P::spill_acc1024_to_compositeRegClass == RC) {
1008-
Opcode = AIE2P::VLDA_CM_SPILL;
1009-
} else if (&AIE2P::spill_acc512_to_compositeRegClass == RC) {
1010-
// I->dump();
1011-
Opcode = AIE2P::VLDA_dmx_lda_bm_spill;
1012-
} else if (&AIE2P::spill_vec1024_to_compositeRegClass == RC) {
1013-
Opcode = AIE2P::VLDA_Y_SPILL;
1014-
} else if (&AIE2P::spill_vec512_to_compositeRegClass == RC) {
1015-
Opcode = AIE2P::VLDA_dmx_lda_x_spill;
10161012
} else if (regClassMatches(AIE2P::eSRegClass, RC, DstReg) ||
10171013
regClassMatches(AIE2P::spill_eS_to_eRRegClass, RC, DstReg)) {
10181014
// Can't spill these directly. Need to bounce through a GPR.
@@ -1082,7 +1078,9 @@ AIE2PInstrInfo::getSpillPseudoExpandInfo(const MachineInstr &MI) const {
10821078
{AIE2P::ST_dms_sts_spill, AIE2P::sub_hi_dim_then_sub_dim_size},
10831079
{AIE2P::ST_dms_sts_spill, AIE2P::sub_hi_dim_then_sub_dim_stride},
10841080
{AIE2P::ST_dms_sts_spill, AIE2P::sub_hi_dim_then_sub_dim_count}};
1085-
1081+
case AIE2P::VST_1024_COMPOSED_REG_SPILL:
1082+
return {{AIE2P::VST_512_COMPOSED_REG_SPILL, AIE2P::sub_512_lo},
1083+
{AIE2P::VST_512_COMPOSED_REG_SPILL, AIE2P::sub_512_hi}};
10861084
case AIE2P::LDA_R_SPILL:
10871085
return {{AIE2P::LDA_dms_lda_spill, AIE2P::NoSubRegister, 4}};
10881086
case AIE2P::VLDA_L_SPILL:
@@ -1132,6 +1130,11 @@ AIE2PInstrInfo::getSpillPseudoExpandInfo(const MachineInstr &MI) const {
11321130
case AIE2P::VST_EX_SPILL:
11331131
return {{AIE2P::VST_dmx_sts_x_spill, AIE2P::sub_bfp16_x},
11341132
{AIE2P::VST_E_SPILL, AIE2P::sub_bfp16_e}};
1133+
case AIE2P::VLDA_1024_COMPOSED_REG_SPILL:
1134+
return {{AIE2P::VLDA_512_COMPOSED_REG_SPILL, AIE2P::sub_512_lo},
1135+
{AIE2P::VLDA_512_COMPOSED_REG_SPILL, AIE2P::sub_512_hi}};
1136+
case AIE2P::VLDA_512_COMPOSED_REG_SPILL:
1137+
return {};
11351138
}
11361139
llvm_unreachable("Un-implemented");
11371140
}
@@ -1222,6 +1225,34 @@ bool AIE2PInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
12221225
MI.eraseFromParent();
12231226
return true;
12241227
}
1228+
case AIE2P::VLDA_512_COMPOSED_REG_SPILL: {
1229+
unsigned int Opcode;
1230+
if (AIE2P::VEC512RegClass.contains(MI.getOperand(0).getReg())) {
1231+
Opcode = AIE2P::VLDA_dmx_lda_x_spill;
1232+
} else if (AIE2P::FIFO512RegClass.contains(MI.getOperand(0).getReg())) {
1233+
Opcode = AIE2P::VLDA_dmx_lda_fifohl_spill;
1234+
} else if (AIE2P::ACC512RegClass.contains(MI.getOperand(0).getReg())) {
1235+
Opcode = AIE2P::VLDA_dmx_lda_bm_spill;
1236+
} else {
1237+
llvm_unreachable("Not a valid register for VST_512_COMPOSED_REG_SPILL");
1238+
}
1239+
MI.setDesc(get(Opcode));
1240+
return false;
1241+
}
1242+
case AIE2P::VST_512_COMPOSED_REG_SPILL: {
1243+
unsigned int Opcode;
1244+
if (AIE2P::VEC512RegClass.contains(MI.getOperand(0).getReg())) {
1245+
Opcode = AIE2P::VST_dmx_sts_x_spill;
1246+
} else if (AIE2P::FIFO512RegClass.contains(MI.getOperand(0).getReg())) {
1247+
Opcode = AIE2P::VST_dmx_sts_fifohl_spill;
1248+
} else if (AIE2P::ACC512RegClass.contains(MI.getOperand(0).getReg())) {
1249+
Opcode = AIE2P::VST_dmx_sts_bm_spill;
1250+
} else {
1251+
llvm_unreachable("Not a valid register for VST_512_COMPOSED_REG_SPILL");
1252+
}
1253+
MI.setDesc(get(Opcode));
1254+
return false;
1255+
}
12251256
}
12261257
return false;
12271258
}

‎llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -321,6 +321,8 @@ def VST_FIFO_SPILL : Pseudo<(outs ), (ins FIFO1024:$src, c16n_step64:$imm), "vst
321321
def VST_PLFR_SPILL : Pseudo<(outs ), (ins ePSRFLdF:$src, c16n_step64:$imm), "vst_plfr_spill", "${src}, [sp, $imm]">;
322322
def VST_EX_SPILL : Pseudo<(outs ), (ins VEC576:$src, c16n_step64:$imm), "vst_ex_spill", "${src}, [sp, $imm]">;
323323
def VST_E_SPILL : Pseudo<(outs ), (ins EXPVEC64:$src, c12n_step4:$imm), "vst_e_spill", "$src, [sp, $imm]">;
324+
def VST_512_COMPOSED_REG_SPILL : Pseudo<(outs ), (ins spill_vec512_to_composite:$src, c16n_step64:$imm), "vst_512_composed_reg_spill", "${src}, [sp, $imm]">;
325+
def VST_1024_COMPOSED_REG_SPILL : Pseudo<(outs ), (ins spill_vec1024_to_composite:$src, c16n_step64:$imm), "vst_512_composed_reg_spill", "${src}, [sp, $imm]">;
324326
}
325327

326328
let mayLoad = true, mayStore = false in {
@@ -335,6 +337,8 @@ def LDA_D_SPILL : Pseudo<(outs eD:$dst), (ins c12n_step4:$imm), "lda_d_spill", "
335337
def LDA_DS_SPILL : Pseudo<(outs eDS:$dst), (ins c12n_step4:$imm), "lda_ds_spill", "${dst}, [sp, $imm]">;
336338
def VLDA_EX_SPILL : Pseudo<(outs VEC576:$dst), (ins c16n_step64:$imm), "vlda_ex_spill", "${dst}, [sp, $imm]">;
337339
def VLDA_E_SPILL : Pseudo<(outs EXPVEC64:$dst), (ins c12n_step4:$imm), "vlda_e_spill", "${dst}, [sp, $imm]">;
340+
def VLDA_512_COMPOSED_REG_SPILL : Pseudo<(outs spill_vec512_to_composite:$dst), (ins c16n_step64:$imm), "vlda_512_composed_reg_spill", "${dst}, [sp, $imm]">;
341+
def VLDA_1024_COMPOSED_REG_SPILL : Pseudo<(outs spill_vec1024_to_composite:$dst), (ins c16n_step64:$imm), "vlda_512_composed_reg_spill", "${dst}, [sp, $imm]">;
338342
}
339343
}
340344

‎llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.cpp‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -194,6 +194,8 @@ bool AIE2PRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
194194
case AIE2P::VST_dmx_sts_bm_spill:
195195
case AIE2P::VST_dmx_sts_fifohl_spill:
196196
case AIE2P::VST_dmx_sts_x_spill:
197+
case AIE2P::VLDA_512_COMPOSED_REG_SPILL:
198+
case AIE2P::VST_512_COMPOSED_REG_SPILL:
197199
MI.getOperand(FIOperandNum).ChangeToImmediate(Offset);
198200
return false;
199201
case AIE2P::LDA_R_SPILL:
@@ -231,10 +233,12 @@ bool AIE2PRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
231233
case AIE2P::VST_CM_SPILL:
232234
case AIE2P::VST_FIFO_SPILL:
233235
case AIE2P::VST_Y_SPILL:
236+
case AIE2P::VST_1024_COMPOSED_REG_SPILL:
234237
case AIE2P::VLDA_DM_SPILL:
235238
case AIE2P::VLDA_CM_SPILL:
236239
case AIE2P::VLDA_FIFO_SPILL:
237240
case AIE2P::VLDA_Y_SPILL:
241+
case AIE2P::VLDA_1024_COMPOSED_REG_SPILL:
238242
MI.getOperand(FIOperandNum).ChangeToImmediate(Offset);
239243
TII->expandSpillPseudo(MI, TRI, /*SubRegOffsetAlign=*/Align(4));
240244
return true;
@@ -488,13 +492,11 @@ AIE2PRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
488492

489493
if (AIE2P::eSRegClass.hasSubClassEq(RC))
490494
return &AIE2P::spill_eS_to_eRRegClass;
491-
if (SpillAccToVecOrAcc && RC == &AIE2P::ACC1024RegClass)
492-
return &AIE2P::spill_acc1024_to_compositeRegClass;
493-
if (SpillAccToVecOrAcc && RC == &AIE2P::ACC512RegClass)
494-
return &AIE2P::spill_acc512_to_compositeRegClass;
495-
if (SpillAccToVecOrAcc && RC == &AIE2P::VEC1024RegClass)
495+
if (SpillAccToVecOrAcc &&
496+
(RC == &AIE2P::ACC1024RegClass || RC == &AIE2P::VEC1024RegClass))
496497
return &AIE2P::spill_vec1024_to_compositeRegClass;
497-
if (SpillAccToVecOrAcc && RC == &AIE2P::VEC512RegClass)
498+
if (SpillAccToVecOrAcc &&
499+
(RC == &AIE2P::ACC512RegClass || RC == &AIE2P::VEC512RegClass))
498500
return &AIE2P::spill_vec512_to_compositeRegClass;
499501
return RC;
500502
}

0 commit comments

Comments
 (0)