From 33118decae745dbf5ffa1c9673a03666ae5fcf86 Mon Sep 17 00:00:00 2001 From: Hamza Khallouki Date: Wed, 12 Feb 2025 17:42:41 +0000 Subject: [PATCH] [AIEX] Properly constrain addressing register classes in PostSelectOptimize to satisfy MachineVerifier --- llvm/lib/Target/AIE/AIE2RegisterInfo.h | 20 ++++++++ llvm/lib/Target/AIE/AIEBaseRegisterInfo.h | 16 +++++++ llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp | 21 ++++++++- llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.h | 21 +++++++++ .../aie2/GlobalISel/duplicate-iterators.mir | 46 +++++++++---------- .../aie2p/GlobalIsel/duplicate-iterators.mir | 44 +++++++++--------- 6 files changed, 121 insertions(+), 47 deletions(-) diff --git a/llvm/lib/Target/AIE/AIE2RegisterInfo.h b/llvm/lib/Target/AIE/AIE2RegisterInfo.h index b18392326d1f..80b148161b6f 100644 --- a/llvm/lib/Target/AIE/AIE2RegisterInfo.h +++ b/llvm/lib/Target/AIE/AIE2RegisterInfo.h @@ -99,6 +99,26 @@ struct AIE2RegisterInfo : public AIE2GenRegisterInfo { const TargetRegisterClass *getAddrCountRegClass() const override { return &AIE2::eDCRegClass; } + + const TargetRegisterClass *getAddrAs32BitPRegClass() const override { + return &AIE2::eP_as_32BitRegClass; + } + + const TargetRegisterClass *getAddrAs32BitDNRegClass() const override { + return &AIE2::eDN_as_32BitRegClass; + } + + const TargetRegisterClass *getAddrAs32BitDJRegClass() const override { + return &AIE2::eDJ_as_32BitRegClass; + } + + const TargetRegisterClass *getAddrAs32BitMRegClass() const override { + return &AIE2::eM_as_32BitRegClass; + } + + const TargetRegisterClass *getAddrAs32BitDCRegClass() const override { + return &AIE2::eDC_as_32BitRegClass; + } }; } // namespace llvm diff --git a/llvm/lib/Target/AIE/AIEBaseRegisterInfo.h b/llvm/lib/Target/AIE/AIEBaseRegisterInfo.h index f8d017c05efe..9b7458a01f4d 100644 --- a/llvm/lib/Target/AIE/AIEBaseRegisterInfo.h +++ b/llvm/lib/Target/AIE/AIEBaseRegisterInfo.h @@ -99,6 +99,22 @@ struct AIEBaseRegisterInfo : public TargetRegisterInfo { virtual const TargetRegisterClass *getAddrCountRegClass() const { llvm_unreachable("Target didn't implement getAddrCountRegClass!"); } + + virtual const TargetRegisterClass *getAddrAs32BitDNRegClass() const { + llvm_unreachable("Target didn't implement getAddrAs32BitDNRegClass!"); + } + virtual const TargetRegisterClass *getAddrAs32BitDJRegClass() const { + llvm_unreachable("Target didn't implement getAddrAs32BitDJRegClass!"); + } + virtual const TargetRegisterClass *getAddrAs32BitPRegClass() const { + llvm_unreachable("Target didn't implement getAddrAs32BitPRegClass!"); + } + virtual const TargetRegisterClass *getAddrAs32BitMRegClass() const { + llvm_unreachable("Target didn't implement getAddrAs32BitMRegClass!"); + } + virtual const TargetRegisterClass *getAddrAs32BitDCRegClass() const { + llvm_unreachable("Target didn't implement getAddrAs32BitDCRegClass!"); + } }; } // namespace llvm diff --git a/llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp b/llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp index 184ce4676eca..937d5a991567 100644 --- a/llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp +++ b/llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp @@ -364,7 +364,7 @@ static void collectIteratorComponentsUsage( static bool tryToDuplicateLoadUse( DenseMap> &LoadUses, SmallSet &NonLoadUses, MachineRegisterInfo &MRI, - const AIEBaseInstrInfo *TII) { + const AIEBaseInstrInfo *TII, const AIEBaseRegisterInfo *TRI) { bool Changed = false; for (auto &RegMILoad : LoadUses) { @@ -377,6 +377,23 @@ static bool tryToDuplicateLoadUse( MachineInstr *DefReg = MRI.getUniqueVRegDef(Reg); MachineBasicBlock::iterator InsertPoint = DefReg->getIterator(); + + // AIE's PseudoMove instruction takes compound register classes which + // contains registers of different sizes. We need to use the right classes + // to avoid the MachineVerifier complaining about mismatching sizes. + auto ConstrainAddrRegClass = [&](Register Reg) { + if (MRI.constrainRegClass(Reg, TRI->getAddrAs32BitDCRegClass()) || + MRI.constrainRegClass(Reg, TRI->getAddrAs32BitDNRegClass()) || + MRI.constrainRegClass(Reg, TRI->getAddrAs32BitDJRegClass()) || + MRI.constrainRegClass(Reg, TRI->getAddrAs32BitMRegClass()) || + MRI.constrainRegClass(Reg, TRI->getAddrAs32BitPRegClass())) + return true; + return false; + }; + + assert(ConstrainAddrRegClass(Reg) && + "Expected an addressing register class"); + Register DstReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); // Here we cannot use COPY, because Machine CSE will run // PerformTrivialCopyPropagation and our work will disappear. @@ -437,7 +454,7 @@ bool duplicateAdressingRegs(MachineBasicBlock &MBB, MachineRegisterInfo &MRI) { // The second part, filter the real useful cases, // registers used in both load and stores (or non load uses). // Then duplicate those registers. - return tryToDuplicateLoadUse(LoadUses, NonLoadUses, MRI, TII); + return tryToDuplicateLoadUse(LoadUses, NonLoadUses, MRI, TII, TRI); } using Operation = AIEBaseInstrInfo::AbstractOp::OperationType; diff --git a/llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.h b/llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.h index 2d41161faa07..07e60edffc23 100644 --- a/llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.h +++ b/llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.h @@ -98,6 +98,27 @@ struct AIE2PRegisterInfo : public AIE2PGenRegisterInfo { const TargetRegisterClass *getAddrCountRegClass() const override { return &AIE2P::eDCRegClass; } + + const TargetRegisterClass *getAddrAs32BitPRegClass() const override { + return &AIE2P::eP_as_32BitRegClass; + } + + const TargetRegisterClass *getAddrAs32BitDNRegClass() const override { + return &AIE2P::eDN_as_32BitRegClass; + } + + const TargetRegisterClass *getAddrAs32BitDJRegClass() const override { + return &AIE2P::eDJ_as_32BitRegClass; + } + + const TargetRegisterClass *getAddrAs32BitMRegClass() const override { + return &AIE2P::eM_as_32BitRegClass; + } + + const TargetRegisterClass *getAddrAs32BitDCRegClass() const override { + return &AIE2P::eDC_as_32BitRegClass; + } + bool isVecOrAccRegClass(const TargetRegisterClass &RC) const override; bool isFifoPhysReg(const Register Reg) const override; diff --git a/llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir b/llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir index 712b084c044b..083447085ef9 100644 --- a/llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir +++ b/llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir @@ -15,7 +15,7 @@ # POST-COALESCER represents the case where we apply the post-select optimization and we # stop after the coalescer. This case shows the optimized version. # COALESCER represents the case where we don't apply the post-select optimization and we -# stop after the coalescer. +# stop after the coalescer. --- name: two2d_descriptors @@ -33,15 +33,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0 - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em = MOV_PD_imm10_pseudo 10 - ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm10_pseudo]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 12 - ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo1]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 14 - ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo2]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm10_pseudo 10 + ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 12 + ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo1]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 14 + ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo2]] ; CHECK-NEXT: [[MOV_PD_imm10_pseudo3:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm10_pseudo4:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 - ; CHECK-NEXT: LoopStart [[COPY2]] + ; CHECK-NEXT: LoopStart [[COPY2]], 0 ; CHECK-NEXT: PseudoJ_jump_imm %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: @@ -77,7 +77,7 @@ body: | ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_stride:ed = PseudoMove [[MOV_PD_imm10_pseudo]].sub_dim_stride ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0 ; POST-COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0 - ; POST-COALESCER-NEXT: LoopStart [[COPY2]] + ; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0 ; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; POST-COALESCER-NEXT: {{ $}} ; POST-COALESCER-NEXT: bb.1: @@ -104,7 +104,7 @@ body: | ; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_stride:ed = MOV_PD_imm10_pseudo 14 ; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0 ; COALESCER-NEXT: undef [[MOV_PD_imm10_pseudo1:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0 - ; COALESCER-NEXT: LoopStart [[COPY2]] + ; COALESCER-NEXT: LoopStart [[COPY2]], 0 ; COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; COALESCER-NEXT: {{ $}} ; COALESCER-NEXT: bb.1: @@ -167,21 +167,21 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0 - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em = MOV_PD_imm10_pseudo 10 - ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm10_pseudo]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 12 - ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo1]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 14 - ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo2]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm10_pseudo 10 + ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 12 + ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo1]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 14 + ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo2]] ; CHECK-NEXT: [[MOV_PD_imm10_pseudo3:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm10_pseudo4:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm10_pseudo5:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm10_pseudo6:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo7:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 16 - ; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo7]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo8:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 18 - ; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo8]] - ; CHECK-NEXT: LoopStart [[COPY2]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo7:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 16 + ; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo7]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo8:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 18 + ; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo8]] + ; CHECK-NEXT: LoopStart [[COPY2]], 0 ; CHECK-NEXT: PseudoJ_jump_imm %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: @@ -225,7 +225,7 @@ body: | ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = PseudoMove [[MOV_PD_imm10_pseudo]].sub_hi_dim_then_sub_dim_size ; POST-COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm10_pseudo 18 ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = PseudoMove [[MOV_PD_imm10_pseudo]].sub_hi_dim_then_sub_dim_stride - ; POST-COALESCER-NEXT: LoopStart [[COPY2]] + ; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0 ; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; POST-COALESCER-NEXT: {{ $}} ; POST-COALESCER-NEXT: bb.1: @@ -260,7 +260,7 @@ body: | ; COALESCER-NEXT: undef [[MOV_PD_imm10_pseudo2:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = MOV_PD_imm10_pseudo 0 ; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = MOV_PD_imm10_pseudo 16 ; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm10_pseudo 18 - ; COALESCER-NEXT: LoopStart [[COPY2]] + ; COALESCER-NEXT: LoopStart [[COPY2]], 0 ; COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; COALESCER-NEXT: {{ $}} ; COALESCER-NEXT: bb.1: diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir index 7f797e3351d7..478e198b45c9 100644 --- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir +++ b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir @@ -33,15 +33,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0 - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em = MOV_PD_imm11_pseudo 10 - ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm11_pseudo]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 12 - ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo1]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 14 - ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo2]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm11_pseudo 10 + ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 12 + ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo1]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 14 + ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo2]] ; CHECK-NEXT: [[MOV_PD_imm11_pseudo3:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm11_pseudo4:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 - ; CHECK-NEXT: LoopStart [[COPY2]] + ; CHECK-NEXT: LoopStart [[COPY2]], 0 ; CHECK-NEXT: PseudoJ_jump_imm %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: @@ -77,7 +77,7 @@ body: | ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_stride:ed = PseudoMove [[MOV_PD_imm11_pseudo]].sub_dim_stride ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0 ; POST-COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0 - ; POST-COALESCER-NEXT: LoopStart [[COPY2]] + ; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0 ; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; POST-COALESCER-NEXT: {{ $}} ; POST-COALESCER-NEXT: bb.1: @@ -104,7 +104,7 @@ body: | ; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_stride:ed = MOV_PD_imm11_pseudo 14 ; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0 ; COALESCER-NEXT: undef [[MOV_PD_imm11_pseudo1:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0 - ; COALESCER-NEXT: LoopStart [[COPY2]] + ; COALESCER-NEXT: LoopStart [[COPY2]], 0 ; COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; COALESCER-NEXT: {{ $}} ; COALESCER-NEXT: bb.1: @@ -167,21 +167,21 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0 - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em = MOV_PD_imm11_pseudo 10 - ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm11_pseudo]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 12 - ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo1]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 14 - ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo2]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm11_pseudo 10 + ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 12 + ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo1]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 14 + ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo2]] ; CHECK-NEXT: [[MOV_PD_imm11_pseudo3:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm11_pseudo4:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm11_pseudo5:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm11_pseudo6:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo7:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 16 - ; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo7]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo8:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 18 - ; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo8]] - ; CHECK-NEXT: LoopStart [[COPY2]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo7:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 16 + ; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo7]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo8:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 18 + ; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo8]] + ; CHECK-NEXT: LoopStart [[COPY2]], 0 ; CHECK-NEXT: PseudoJ_jump_imm %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: @@ -225,7 +225,7 @@ body: | ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = PseudoMove [[MOV_PD_imm11_pseudo]].sub_hi_dim_then_sub_dim_size ; POST-COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm11_pseudo 18 ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = PseudoMove [[MOV_PD_imm11_pseudo]].sub_hi_dim_then_sub_dim_stride - ; POST-COALESCER-NEXT: LoopStart [[COPY2]] + ; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0 ; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; POST-COALESCER-NEXT: {{ $}} ; POST-COALESCER-NEXT: bb.1: @@ -260,7 +260,7 @@ body: | ; COALESCER-NEXT: undef [[MOV_PD_imm11_pseudo2:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = MOV_PD_imm11_pseudo 0 ; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = MOV_PD_imm11_pseudo 16 ; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm11_pseudo 18 - ; COALESCER-NEXT: LoopStart [[COPY2]] + ; COALESCER-NEXT: LoopStart [[COPY2]], 0 ; COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; COALESCER-NEXT: {{ $}} ; COALESCER-NEXT: bb.1: