[AIEX] Add AA support for stack fixed objects

Author: andcarminati

llvm/lib/Target/AIE/AIEBaseInstrInfo.cpp

@@ -1448,3 +1448,61 @@ void AIEBaseInstrInfo::insertSelect(MachineBasicBlock &MBB,
       .addReg(Support->getSelectSrcOperand(InputOperands, 1))
       .addReg(Support->getSelectSrcOperand(InputOperands, 2));
 }
+
+bool AIEBaseInstrInfo::areMemAccessesTriviallyDisjoint(
+    const MachineInstr &MIa, const MachineInstr &MIb) const {
+  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
+    return false;
+
+  // If mem-operands show that the same address Value is used by both
+  // instructions, check for non-overlapping offsets and widths.
+  const MachineMemOperand *MMOa = *MIa.memoperands_begin();
+  const MachineMemOperand *MMOb = *MIb.memoperands_begin();
+
+  auto CheckOverlapping = [=](int64_t OffsetA, int64_t OffsetB) {
+    const LocationSize WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
+    const int64_t LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
+    const int64_t HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
+    const LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
+    return (LowWidth.hasValue() &&
+            LowOffset + (int64_t)LowWidth.getValue() <= HighOffset);
+  };
+
+  int64_t MMOOffsetA = MMOa->getOffset();
+  int64_t MMOOffsetB = MMOb->getOffset();
+
+  const Value *VALa = MMOa->getValue();
+  const Value *VALb = MMOb->getValue();
+  const bool SameValue = (VALa && VALb && (VALa == VALb));
+  if (SameValue)
+    return CheckOverlapping(MMOOffsetA, MMOOffsetB);
+
+  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
+  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
+
+  const bool WithBothPseudoSources = PSVa && PSVb;
+  if (!WithBothPseudoSources)
+    return false;
+
+  const bool SamePseudoSource = PSVa == PSVb;
+  if (SamePseudoSource)
+    return CheckOverlapping(MMOOffsetB, MMOOffsetB);
+
+  const FixedStackPseudoSourceValue *FixedStackA =
+      dyn_cast<FixedStackPseudoSourceValue>(PSVa);
+  const FixedStackPseudoSourceValue *FixedStackB =
+      dyn_cast<FixedStackPseudoSourceValue>(PSVb);
+
+  // If we have different fixed stack objects, we have disjoint access
+  // when offsets are different and we don't have any partial overlap
+  // (SameVal check).
+  const bool WithBothFixedStackObj = FixedStackA && FixedStackB;
+  if (!WithBothFixedStackObj)
+    return false;
+
+  const MachineFrameInfo &MFI = MIa.getMF()->getFrameInfo();
+  const int64_t ObjOffsetA = MFI.getObjectOffset(FixedStackA->getFrameIndex());
+  const int64_t ObjOffsetB = MFI.getObjectOffset(FixedStackB->getFrameIndex());
+
+  return CheckOverlapping(ObjOffsetA, ObjOffsetB);
+}

llvm/lib/Target/AIE/AIEBaseInstrInfo.h

@@ -869,6 +869,9 @@ struct AIEBaseInstrInfo : public TargetInstrInfo {
                     const DebugLoc &dl, Register DestReg,
                     ArrayRef<MachineOperand> Cond, Register TrueReg,
                     Register FalseReg) const override;
+
+  bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
+                                       const MachineInstr &MIb) const override;
 };
 
 template <unsigned NumEncodingBits, unsigned Step>

llvm/test/CodeGen/AIE/aie2p/schedule/pre_ra/stackAA-presched.mir

@@ -28,6 +28,7 @@
 # In this case, we have five fixed stack objects: 0, that is aliasing (same offset)
 # with 2 and 1 that is aliasing with 3. We also have an object 4 that partially alias
 # with 0 and 2.
+# Note: this tests AIEBaseInstrInfo::areMemAccessesTriviallyDisjoint()
 
 ---
 name:            load_and_store_chain
@@ -72,8 +73,8 @@ body:             |
     ; CHECK: SU(1):   %1:er = LDA_dms_lda_idx_imm %0:ep, 0 :: (invariant load (s32) from %fixed-stack.1)
     ; CHECK: Successors:
     ; CHECK: SU(6): Data Latency=7 Reg=%1
-    ; CHECK: SU(10): Ord  Latency=0 Memory
-    ; CHECK: SU(8): Ord  Latency=0 Memory
+    ; CHECK-NOT: SU(10): Ord  Latency=0 Memory
+    ; CHECK-NOT: SU(8): Ord  Latency=0 Memory
     ; CHECK: SU(6): Ord  Latency=0 Memory
 
     ; CHECK: SU(3):   %3:er = LDA_dms_lda_idx_imm %2:ep, 0 :: (invariant load (s32) from %fixed-stack.2, align 8)
@@ -82,7 +83,7 @@ body:             |
     ; CHECK: SU(8): Data Latency=7 Reg=%3
     ; CHECK: SU(10): Ord  Latency=0 Memory
     ; CHECK: SU(8): Ord  Latency=0 Memory
-    ; CHECK: SU(6): Ord  Latency=0 Memory
+    ; CHECK-NOT: SU(6): Ord  Latency=0 Memory
 
     ; CHECK: SU(6):   ST_dms_sts_idx_imm %1:er, %4:ep, 0 :: (store (s32) into %fixed-stack.3, align 32)
     ; CHECK: SU(8):   ST_dms_sts_idx_imm %3:er, %5:ep, 0 :: (store (s32) into %fixed-stack.4)