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[AIE2] NFC: Add baseline test with critical CM reg pressure
In a follow-up commit, the premisched will re-order the instructions to reduce the pressure and avoid spills during RA.
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‎llvm/test/CodeGen/AIE/aie2/schedule/pre_ra/add2d_inner.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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#
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# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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# See https://llvm.org/LICENSE.txt for license information.
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# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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#
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# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
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# RUN: llc -march=aie2 -run-pass=machine-scheduler %s -o - | FileCheck %s
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# This represents the innermost loop of Add2D after SW pipelining.
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# We should see most of the VLDA.UPS instructions move down in the loop
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# BB to reduce the reg pressure and avoid spills. They can later be moved back
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# up by the post-RA scheduler. This should also make the 4 acc1024 COPY
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# instructions coalesce-able.
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---
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name: add2d_innermost
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: add2d_innermost
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $p0, $m0, $cm0, $cm1, $s0, $d1, $x0, $r0, $d0_3d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:em = COPY $m0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:acc1024 = COPY $cm0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:acc1024 = COPY $cm0
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:acc1024 = COPY $cm0
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:acc1024 = COPY $cm0
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:acc1024 = COPY $cm0
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:acc1024 = COPY $cm0
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:acc1024 = COPY $cm0
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; CHECK-NEXT: [[COPY8:%[0-9]+]]:acc1024 = COPY $cm0
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; CHECK-NEXT: [[COPY9:%[0-9]+]]:ep_as_32bit = COPY $p0
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; CHECK-NEXT: [[COPY10:%[0-9]+]]:ep_as_32bit = COPY $p0
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:ep_as_32bit = COPY $p0
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; CHECK-NEXT: [[COPY12:%[0-9]+]]:eds = COPY $d0_3d
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; CHECK-NEXT: [[COPY13:%[0-9]+]]:er = COPY $r0
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; CHECK-NEXT: [[COPY14:%[0-9]+]]:er = COPY $r0
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; CHECK-NEXT: [[COPY15:%[0-9]+]]:mss = COPY $s0
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; CHECK-NEXT: [[COPY16:%[0-9]+]]:mss = COPY $s0
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; CHECK-NEXT: PseudoJ_jump_imm %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY17:%[0-9]+]]:acc1024 = COPY [[COPY4]]
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; CHECK-NEXT: [[VADD:%[0-9]+]]:acc1024 = VADD [[COPY5]], [[COPY17]], [[COPY14]]
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; CHECK-NEXT: [[COPY18:%[0-9]+]]:acc1024 = COPY [[COPY3]]
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; CHECK-NEXT: [[VADD1:%[0-9]+]]:acc1024 = VADD [[COPY6]], [[COPY18]], [[COPY14]]
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; CHECK-NEXT: [[COPY19:%[0-9]+]]:acc1024 = COPY [[COPY2]]
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:acc1024, [[COPY9:%[0-9]+]]:ep_as_32bit = VLDA_UPS_S32_D8_ag_pstm_nrm [[COPY15]], [[COPY9]], [[COPY]], implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 64)
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; CHECK-NEXT: [[VADD2:%[0-9]+]]:acc1024 = VADD [[COPY7]], [[COPY19]], [[COPY14]]
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; CHECK-NEXT: [[COPY20:%[0-9]+]]:acc1024 = COPY [[COPY1]]
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:acc1024, [[COPY9:%[0-9]+]]:ep_as_32bit = VLDA_UPS_S32_D8_ag_pstm_nrm [[COPY15]], [[COPY9]], [[COPY]], implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 64)
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; CHECK-NEXT: [[VADD3:%[0-9]+]]:acc1024 = VADD [[COPY8]], [[COPY20]], [[COPY14]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:acc1024, [[COPY9:%[0-9]+]]:ep_as_32bit = VLDA_UPS_S32_D8_ag_pstm_nrm [[COPY15]], [[COPY9]], [[COPY]], implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 64)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:acc1024, [[COPY9:%[0-9]+]]:ep_as_32bit = VLDA_UPS_S32_D8_ag_pstm_nrm [[COPY15]], [[COPY9]], [[COPY]], implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 64)
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:ep_as_32bit = VST_SRS_D8_S32_ag_pstm_nrm_imm [[COPY11]], 32, [[VADD]], [[COPY16]], implicit-def $srsrs_of, implicit $crsat, implicit $crrnd, implicit $crsrssign :: (store (<32 x s8>) into stack - 128)
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:acc1024, [[COPY10:%[0-9]+]]:ep_as_32bit, [[COPY12:%[0-9]+]].sub_dim_count:eds, [[COPY12:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = VLDA_3D_UPS_S32_D8 [[COPY15]], [[COPY10]], [[COPY12]], implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 32)
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:ep_as_32bit = VST_SRS_D8_S32_ag_pstm_nrm_imm [[COPY11]], 32, [[VADD1]], [[COPY16]], implicit-def $srsrs_of, implicit $crsat, implicit $crrnd, implicit $crsrssign :: (store (<32 x s8>) into stack - 128)
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:acc1024, [[COPY10:%[0-9]+]]:ep_as_32bit, [[COPY12:%[0-9]+]].sub_dim_count:eds, [[COPY12:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = VLDA_3D_UPS_S32_D8 [[COPY15]], [[COPY10]], [[COPY12]], implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 32)
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:ep_as_32bit = VST_SRS_D8_S32_ag_pstm_nrm_imm [[COPY11]], 32, [[VADD2]], [[COPY16]], implicit-def $srsrs_of, implicit $crsat, implicit $crrnd, implicit $crsrssign :: (store (<32 x s8>) into stack - 128)
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:acc1024, [[COPY10:%[0-9]+]]:ep_as_32bit, [[COPY12:%[0-9]+]].sub_dim_count:eds, [[COPY12:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = VLDA_3D_UPS_S32_D8 [[COPY15]], [[COPY10]], [[COPY12]], implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 32)
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:ep_as_32bit = VST_SRS_D8_S32_ag_pstm_nrm_imm [[COPY11]], 32, [[VADD3]], [[COPY16]], implicit-def $srsrs_of, implicit $crsat, implicit $crrnd, implicit $crsrssign :: (store (<32 x s8>) into stack - 128)
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; CHECK-NEXT: [[COPY8:%[0-9]+]]:acc1024, [[COPY10:%[0-9]+]]:ep_as_32bit, [[COPY12:%[0-9]+]].sub_dim_count:eds, [[COPY12:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = VLDA_3D_UPS_S32_D8 [[COPY15]], [[COPY10]], [[COPY12]], implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 32)
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; CHECK-NEXT: [[COPY13:%[0-9]+]]:er = ADD_add_r_ri [[COPY13]], -4, implicit-def dead $srcarry
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; CHECK-NEXT: PseudoJNZ [[COPY13]], %bb.1
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; CHECK-NEXT: PseudoJ_jump_imm %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: PseudoRET implicit $lr
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bb.0.entry:
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liveins: $p0, $m0, $cm0, $cm1, $s0, $d1, $x0, $r0, $d0_3d
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%367:acc1024 = COPY $cm0
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%365:acc1024 = COPY $cm0
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%363:acc1024 = COPY $cm0
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%361:acc1024 = COPY $cm0
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%362:acc1024 = COPY $cm0
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%364:acc1024 = COPY $cm0
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%366:acc1024 = COPY $cm0
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%368:acc1024 = COPY $cm0
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%248:mss = COPY $s0
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%245:mss = COPY $s0
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%355:ep_as_32bit = COPY $p0
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%358:ep_as_32bit = COPY $p0
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%359:ep_as_32bit = COPY $p0
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%82:em = COPY $m0
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%272:eds = COPY $d0_3d
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%360:er = COPY $r0
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%206:er = COPY $r0
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PseudoJ_jump_imm %bb.1
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bb.1:
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successors: %bb.2(0x04000000), %bb.1(0x7c000000)
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%327:acc1024 = COPY %367
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%325:acc1024 = COPY %365
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%323:acc1024 = COPY %363
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%321:acc1024 = COPY %361
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%361:acc1024, %355:ep_as_32bit = VLDA_UPS_S32_D8_ag_pstm_nrm %248, %355, %82, implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 64)
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%360:er = ADD_add_r_ri %360, -4, implicit-def dead $srcarry
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%281:acc1024 = VADD %362, %321, %206
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%363:acc1024, %355:ep_as_32bit = VLDA_UPS_S32_D8_ag_pstm_nrm %248, %355, %82, implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 64)
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%284:acc1024 = VADD %364, %323, %206
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%365:acc1024, %355:ep_as_32bit = VLDA_UPS_S32_D8_ag_pstm_nrm %248, %355, %82, implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 64)
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%287:acc1024 = VADD %366, %325, %206
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%367:acc1024, %355:ep_as_32bit = VLDA_UPS_S32_D8_ag_pstm_nrm %248, %355, %82, implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 64)
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%362:acc1024, %358:ep_as_32bit, %272.sub_dim_count:eds, %272.sub_hi_dim_then_sub_dim_count:eds = VLDA_3D_UPS_S32_D8 %248, %358, %272, implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 32)
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%295:acc1024 = VADD %368, %327, %206
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%364:acc1024, %358:ep_as_32bit, %272.sub_dim_count:eds, %272.sub_hi_dim_then_sub_dim_count:eds = VLDA_3D_UPS_S32_D8 %248, %358, %272, implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 32)
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%366:acc1024, %358:ep_as_32bit, %272.sub_dim_count:eds, %272.sub_hi_dim_then_sub_dim_count:eds = VLDA_3D_UPS_S32_D8 %248, %358, %272, implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 32)
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%359:ep_as_32bit = VST_SRS_D8_S32_ag_pstm_nrm_imm %359, 32, %281, %245, implicit-def $srsrs_of, implicit $crsat, implicit $crrnd, implicit $crsrssign :: (store (<32 x s8>) into stack - 128)
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%359:ep_as_32bit = VST_SRS_D8_S32_ag_pstm_nrm_imm %359, 32, %284, %245, implicit-def $srsrs_of, implicit $crsat, implicit $crrnd, implicit $crsrssign :: (store (<32 x s8>) into stack - 128)
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%368:acc1024, %358:ep_as_32bit, %272.sub_dim_count:eds, %272.sub_hi_dim_then_sub_dim_count:eds = VLDA_3D_UPS_S32_D8 %248, %358, %272, implicit-def $srups_of, implicit $crsat, implicit $crupssign :: (load (<32 x s8>) from stack - 32)
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%359:ep_as_32bit = VST_SRS_D8_S32_ag_pstm_nrm_imm %359, 32, %287, %245, implicit-def $srsrs_of, implicit $crsat, implicit $crrnd, implicit $crsrssign :: (store (<32 x s8>) into stack - 128)
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%359:ep_as_32bit = VST_SRS_D8_S32_ag_pstm_nrm_imm %359, 32, %295, %245, implicit-def $srsrs_of, implicit $crsat, implicit $crrnd, implicit $crsrssign :: (store (<32 x s8>) into stack - 128)
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PseudoJNZ %360, %bb.1
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PseudoJ_jump_imm %bb.2
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bb.2:
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PseudoRET implicit $lr
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...

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