From ed080290fb48e8007a1defc3f35a437cebee5e70 Mon Sep 17 00:00:00 2001 From: Hamza Khallouki Date: Wed, 12 Feb 2025 17:42:41 +0000 Subject: [PATCH] [AIEX] Properly constrain addressing register classes in PostSelectOptimize to satisfy MachineVerifier --- llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp | 20 +++++-- .../aie2/GlobalISel/duplicate-iterators.mir | 54 +++++++++---------- .../aie2p/GlobalIsel/duplicate-iterators.mir | 52 +++++++++--------- 3 files changed, 68 insertions(+), 58 deletions(-) diff --git a/llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp b/llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp index 184ce4676eca..e9dc139dd7ec 100644 --- a/llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp +++ b/llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp @@ -33,6 +33,7 @@ #include "AIE2.h" #include "AIE2InstrInfo.h" #include "AIE2RegisterInfo.h" +#include "AIEBaseRegisterBankInfo.h" #include "AIEBaseRegisterInfo.h" #include "AIECombinerHelper.h" #include "Utils/AIELoopUtils.h" @@ -364,7 +365,8 @@ static void collectIteratorComponentsUsage( static bool tryToDuplicateLoadUse( DenseMap> &LoadUses, SmallSet &NonLoadUses, MachineRegisterInfo &MRI, - const AIEBaseInstrInfo *TII) { + const AIEBaseInstrInfo *TII, const AIEBaseRegisterInfo *TRI, + const AIEBaseRegisterBankInfo *RBI) { bool Changed = false; for (auto &RegMILoad : LoadUses) { @@ -381,9 +383,15 @@ static bool tryToDuplicateLoadUse( // Here we cannot use COPY, because Machine CSE will run // PerformTrivialCopyPropagation and our work will disappear. // smoothly. - BuildMI(*DefReg->getParent(), ++InsertPoint, DefReg->getDebugLoc(), - TII->get(TII->getPseudoMoveOpcode()), DstReg) - .addReg(Reg); + MachineInstr *MI = + BuildMI(*DefReg->getParent(), ++InsertPoint, DefReg->getDebugLoc(), + TII->get(TII->getPseudoMoveOpcode()), DstReg) + .addReg(Reg); + + // AIE's PseudoMove instruction takes compound register classes which + // contains registers of different sizes. We need to use the right classes + // to avoid the MachineVerifier complaining about mismatching sizes. + constrainSelectedInstRegOperands(*MI, *TII, *TRI, *RBI); for (MachineInstr *UseMI : RegMILoad.second) { for (auto &Operand : UseMI->operands()) { @@ -407,6 +415,8 @@ bool duplicateAdressingRegs(MachineBasicBlock &MBB, MachineRegisterInfo &MRI) { static_cast(ST.getInstrInfo()); const AIEBaseRegisterInfo *TRI = static_cast(ST.getRegisterInfo()); + const AIEBaseRegisterBankInfo *RBI = + static_cast(ST.getRegBankInfo()); assert(TII->getPseudoMoveOpcode() && "Target must have a PseudoMove instruction"); @@ -437,7 +447,7 @@ bool duplicateAdressingRegs(MachineBasicBlock &MBB, MachineRegisterInfo &MRI) { // The second part, filter the real useful cases, // registers used in both load and stores (or non load uses). // Then duplicate those registers. - return tryToDuplicateLoadUse(LoadUses, NonLoadUses, MRI, TII); + return tryToDuplicateLoadUse(LoadUses, NonLoadUses, MRI, TII, TRI, RBI); } using Operation = AIEBaseInstrInfo::AbstractOp::OperationType; diff --git a/llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir b/llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir index 712b084c044b..47cd833bea16 100644 --- a/llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir +++ b/llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir @@ -4,18 +4,18 @@ # See https://llvm.org/LICENSE.txt for license information. # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception # -# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates +# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates -# RUN: llc -mtriple aie2 -run-pass=aie-post-select-optimize %s -o - | FileCheck %s -# RUN: llc -mtriple aie2 -start-before=aie-post-select-optimize -stop-after=register-coalescer \ +# RUN: llc -mtriple aie2 -run-pass=aie-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple aie2 -start-before=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \ # RUN: %s -o - | FileCheck %s -check-prefix=POST-COALESCER -# RUN: llc -mtriple aie2 -start-after=aie-post-select-optimize -stop-after=register-coalescer \ +# RUN: llc -mtriple aie2 -start-after=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \ # RUN: %s -o - | FileCheck %s -check-prefix=COALESCER # POST-COALESCER represents the case where we apply the post-select optimization and we # stop after the coalescer. This case shows the optimized version. # COALESCER represents the case where we don't apply the post-select optimization and we -# stop after the coalescer. +# stop after the coalescer. --- name: two2d_descriptors @@ -33,15 +33,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0 - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em = MOV_PD_imm10_pseudo 10 - ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm10_pseudo]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 12 - ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo1]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 14 - ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo2]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm10_pseudo 10 + ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 12 + ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo1]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 14 + ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo2]] ; CHECK-NEXT: [[MOV_PD_imm10_pseudo3:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm10_pseudo4:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 - ; CHECK-NEXT: LoopStart [[COPY2]] + ; CHECK-NEXT: LoopStart [[COPY2]], 0 ; CHECK-NEXT: PseudoJ_jump_imm %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: @@ -77,7 +77,7 @@ body: | ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_stride:ed = PseudoMove [[MOV_PD_imm10_pseudo]].sub_dim_stride ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0 ; POST-COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0 - ; POST-COALESCER-NEXT: LoopStart [[COPY2]] + ; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0 ; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; POST-COALESCER-NEXT: {{ $}} ; POST-COALESCER-NEXT: bb.1: @@ -104,7 +104,7 @@ body: | ; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_stride:ed = MOV_PD_imm10_pseudo 14 ; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0 ; COALESCER-NEXT: undef [[MOV_PD_imm10_pseudo1:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0 - ; COALESCER-NEXT: LoopStart [[COPY2]] + ; COALESCER-NEXT: LoopStart [[COPY2]], 0 ; COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; COALESCER-NEXT: {{ $}} ; COALESCER-NEXT: bb.1: @@ -167,21 +167,21 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0 - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em = MOV_PD_imm10_pseudo 10 - ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm10_pseudo]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 12 - ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo1]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 14 - ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo2]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm10_pseudo 10 + ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 12 + ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo1]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 14 + ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo2]] ; CHECK-NEXT: [[MOV_PD_imm10_pseudo3:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm10_pseudo4:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm10_pseudo5:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm10_pseudo6:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0 - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo7:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 16 - ; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo7]] - ; CHECK-NEXT: [[MOV_PD_imm10_pseudo8:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 18 - ; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo8]] - ; CHECK-NEXT: LoopStart [[COPY2]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo7:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 16 + ; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo7]] + ; CHECK-NEXT: [[MOV_PD_imm10_pseudo8:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 18 + ; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo8]] + ; CHECK-NEXT: LoopStart [[COPY2]], 0 ; CHECK-NEXT: PseudoJ_jump_imm %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: @@ -225,7 +225,7 @@ body: | ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = PseudoMove [[MOV_PD_imm10_pseudo]].sub_hi_dim_then_sub_dim_size ; POST-COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm10_pseudo 18 ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = PseudoMove [[MOV_PD_imm10_pseudo]].sub_hi_dim_then_sub_dim_stride - ; POST-COALESCER-NEXT: LoopStart [[COPY2]] + ; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0 ; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; POST-COALESCER-NEXT: {{ $}} ; POST-COALESCER-NEXT: bb.1: @@ -260,7 +260,7 @@ body: | ; COALESCER-NEXT: undef [[MOV_PD_imm10_pseudo2:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = MOV_PD_imm10_pseudo 0 ; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = MOV_PD_imm10_pseudo 16 ; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm10_pseudo 18 - ; COALESCER-NEXT: LoopStart [[COPY2]] + ; COALESCER-NEXT: LoopStart [[COPY2]], 0 ; COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; COALESCER-NEXT: {{ $}} ; COALESCER-NEXT: bb.1: diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir index 7f797e3351d7..273ca83b9914 100644 --- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir +++ b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir @@ -4,12 +4,12 @@ # See https://llvm.org/LICENSE.txt for license information. # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception # -# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates +# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates -# RUN: llc -mtriple aie2p -run-pass=aie-post-select-optimize %s -o - | FileCheck %s -# RUN: llc -mtriple aie2p -start-before=aie-post-select-optimize -stop-after=register-coalescer \ +# RUN: llc -mtriple aie2p -run-pass=aie-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple aie2p -start-before=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \ # RUN: %s -o - | FileCheck %s -check-prefix=POST-COALESCER -# RUN: llc -mtriple aie2p -start-after=aie-post-select-optimize -stop-after=register-coalescer \ +# RUN: llc -mtriple aie2p -start-after=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \ # RUN: %s -o - | FileCheck %s -check-prefix=COALESCER # POST-COALESCER represents the case where we apply the post-select optimization and we @@ -33,15 +33,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0 - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em = MOV_PD_imm11_pseudo 10 - ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm11_pseudo]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 12 - ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo1]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 14 - ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo2]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm11_pseudo 10 + ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 12 + ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo1]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 14 + ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo2]] ; CHECK-NEXT: [[MOV_PD_imm11_pseudo3:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm11_pseudo4:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 - ; CHECK-NEXT: LoopStart [[COPY2]] + ; CHECK-NEXT: LoopStart [[COPY2]], 0 ; CHECK-NEXT: PseudoJ_jump_imm %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: @@ -77,7 +77,7 @@ body: | ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_stride:ed = PseudoMove [[MOV_PD_imm11_pseudo]].sub_dim_stride ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0 ; POST-COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0 - ; POST-COALESCER-NEXT: LoopStart [[COPY2]] + ; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0 ; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; POST-COALESCER-NEXT: {{ $}} ; POST-COALESCER-NEXT: bb.1: @@ -104,7 +104,7 @@ body: | ; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_stride:ed = MOV_PD_imm11_pseudo 14 ; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0 ; COALESCER-NEXT: undef [[MOV_PD_imm11_pseudo1:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0 - ; COALESCER-NEXT: LoopStart [[COPY2]] + ; COALESCER-NEXT: LoopStart [[COPY2]], 0 ; COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; COALESCER-NEXT: {{ $}} ; COALESCER-NEXT: bb.1: @@ -167,21 +167,21 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0 - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em = MOV_PD_imm11_pseudo 10 - ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm11_pseudo]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 12 - ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo1]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 14 - ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo2]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm11_pseudo 10 + ; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 12 + ; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo1]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 14 + ; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo2]] ; CHECK-NEXT: [[MOV_PD_imm11_pseudo3:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm11_pseudo4:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm11_pseudo5:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 ; CHECK-NEXT: [[MOV_PD_imm11_pseudo6:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0 - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo7:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 16 - ; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo7]] - ; CHECK-NEXT: [[MOV_PD_imm11_pseudo8:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 18 - ; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo8]] - ; CHECK-NEXT: LoopStart [[COPY2]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo7:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 16 + ; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo7]] + ; CHECK-NEXT: [[MOV_PD_imm11_pseudo8:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 18 + ; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo8]] + ; CHECK-NEXT: LoopStart [[COPY2]], 0 ; CHECK-NEXT: PseudoJ_jump_imm %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: @@ -225,7 +225,7 @@ body: | ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = PseudoMove [[MOV_PD_imm11_pseudo]].sub_hi_dim_then_sub_dim_size ; POST-COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm11_pseudo 18 ; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = PseudoMove [[MOV_PD_imm11_pseudo]].sub_hi_dim_then_sub_dim_stride - ; POST-COALESCER-NEXT: LoopStart [[COPY2]] + ; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0 ; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; POST-COALESCER-NEXT: {{ $}} ; POST-COALESCER-NEXT: bb.1: @@ -260,7 +260,7 @@ body: | ; COALESCER-NEXT: undef [[MOV_PD_imm11_pseudo2:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = MOV_PD_imm11_pseudo 0 ; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = MOV_PD_imm11_pseudo 16 ; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm11_pseudo 18 - ; COALESCER-NEXT: LoopStart [[COPY2]] + ; COALESCER-NEXT: LoopStart [[COPY2]], 0 ; COALESCER-NEXT: PseudoJ_jump_imm %bb.1 ; COALESCER-NEXT: {{ $}} ; COALESCER-NEXT: bb.1: