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[TableGen] Change DefInit::Def to a const Record pointer (llvm#110747)
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This change undoes a const_cast<> introduced in an earlier change to
help transition to const pointers. It is a part of effort to have better
const correctness in TableGen backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
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jurahul authored Oct 2, 2024
1 parent 1905cdb commit d256b9e
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Showing 16 changed files with 67 additions and 63 deletions.
2 changes: 1 addition & 1 deletion clang/utils/TableGen/ClangOptionDocEmitter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@ const unsigned UnlimitedArgs = unsigned(-1);

// Get the number of arguments expected for an option, or -1 if any number of
// arguments are accepted.
unsigned getNumArgsForKind(Record *OptionKind, const Record *Option) {
unsigned getNumArgsForKind(const Record *OptionKind, const Record *Option) {
return StringSwitch<unsigned>(OptionKind->getName())
.Cases("KIND_JOINED", "KIND_JOINED_OR_SEPARATE", "KIND_SEPARATE", 1)
.Cases("KIND_REMAINING_ARGS", "KIND_REMAINING_ARGS_JOINED",
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6 changes: 4 additions & 2 deletions llvm/include/llvm/TableGen/DirectiveEmitter.h
Original file line number Diff line number Diff line change
Expand Up @@ -155,9 +155,11 @@ class Directive : public BaseRecord {
return Def->getValueAsListOfDefs("leafConstructs");
}

Record *getAssociation() const { return Def->getValueAsDef("association"); }
const Record *getAssociation() const {
return Def->getValueAsDef("association");
}

Record *getCategory() const { return Def->getValueAsDef("category"); }
const Record *getCategory() const { return Def->getValueAsDef("category"); }
};

// Wrapper class that contains Clause's information defined in DirectiveBase.td
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18 changes: 9 additions & 9 deletions llvm/include/llvm/TableGen/Record.h
Original file line number Diff line number Diff line change
Expand Up @@ -783,7 +783,7 @@ class ListInit final : public TypedInit, public FoldingSetNode,
return cast<ListRecTy>(getType())->getElementType();
}

Record *getElementAsRecord(unsigned i) const;
const Record *getElementAsRecord(unsigned i) const;

Init *convertInitializerTo(const RecTy *Ty) const override;

Expand Down Expand Up @@ -1316,9 +1316,9 @@ class VarBitInit final : public TypedInit {
class DefInit : public TypedInit {
friend class Record;

Record *Def;
const Record *Def;

explicit DefInit(Record *D);
explicit DefInit(const Record *D);

public:
DefInit(const DefInit &) = delete;
Expand All @@ -1330,7 +1330,7 @@ class DefInit : public TypedInit {

Init *convertInitializerTo(const RecTy *Ty) const override;

Record *getDef() const { return Def; }
const Record *getDef() const { return Def; }

const RecTy *getFieldType(StringInit *FieldName) const override;

Expand Down Expand Up @@ -1473,7 +1473,7 @@ class DagInit final : public TypedInit, public FoldingSetNode,
void Profile(FoldingSetNodeID &ID) const;

Init *getOperator() const { return Val; }
Record *getOperatorAsDef(ArrayRef<SMLoc> Loc) const;
const Record *getOperatorAsDef(ArrayRef<SMLoc> Loc) const;

StringInit *getName() const { return ValName; }

Expand Down Expand Up @@ -1660,7 +1660,7 @@ class Record {
// this record.
SmallVector<SMLoc, 4> Locs;
SmallVector<SMLoc, 0> ForwardDeclarationLocs;
SmallVector<SMRange, 0> ReferenceLocs;
mutable SmallVector<SMRange, 0> ReferenceLocs;
SmallVector<Init *, 0> TemplateArgs;
SmallVector<RecordVal, 0> Values;
SmallVector<AssertionInfo, 0> Assertions;
Expand Down Expand Up @@ -1729,7 +1729,7 @@ class Record {
}

/// Add a reference to this record value.
void appendReferenceLoc(SMRange Loc) { ReferenceLocs.push_back(Loc); }
void appendReferenceLoc(SMRange Loc) const { ReferenceLocs.push_back(Loc); }

/// Return the references of this record value.
ArrayRef<SMRange> getReferenceLocs() const { return ReferenceLocs; }
Expand Down Expand Up @@ -1931,13 +1931,13 @@ class Record {
/// This method looks up the specified field and returns its value as a
/// Record, throwing an exception if the field does not exist or if the value
/// is not the right type.
Record *getValueAsDef(StringRef FieldName) const;
const Record *getValueAsDef(StringRef FieldName) const;

/// This method looks up the specified field and returns its value as a
/// Record, returning null if the field exists but is "uninitialized" (i.e.
/// set to `?`), and throwing an exception if the field does not exist or if
/// its value is not the right type.
Record *getValueAsOptionalDef(StringRef FieldName) const;
const Record *getValueAsOptionalDef(StringRef FieldName) const;

/// This method looks up the specified field and returns its value as a bit,
/// throwing an exception if the field does not exist or if the value is not
Expand Down
19 changes: 9 additions & 10 deletions llvm/lib/TableGen/Record.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -746,7 +746,7 @@ Init *ListInit::convertInitializerTo(const RecTy *Ty) const {
return nullptr;
}

Record *ListInit::getElementAsRecord(unsigned i) const {
const Record *ListInit::getElementAsRecord(unsigned i) const {
assert(i < NumValues && "List element index out of range!");
DefInit *DI = dyn_cast<DefInit>(getElement(i));
if (!DI)
Expand Down Expand Up @@ -1713,7 +1713,7 @@ Init *TernOpInit::Fold(Record *CurRec) const {
StringInit *RHSs = dyn_cast<StringInit>(RHS);

if (LHSd && MHSd && RHSd) {
Record *Val = RHSd->getDef();
const Record *Val = RHSd->getDef();
if (LHSd->getAsString() == RHSd->getAsString())
Val = MHSd->getDef();
return Val->getDefInit();
Expand Down Expand Up @@ -2265,7 +2265,7 @@ Init *VarBitInit::resolveReferences(Resolver &R) const {
return const_cast<VarBitInit*>(this);
}

DefInit::DefInit(Record *D)
DefInit::DefInit(const Record *D)
: TypedInit(IK_DefInit, D->getType()), Def(D) {}

Init *DefInit::convertInitializerTo(const RecTy *Ty) const {
Expand Down Expand Up @@ -2445,7 +2445,7 @@ Init *FieldInit::resolveReferences(Resolver &R) const {

Init *FieldInit::Fold(Record *CurRec) const {
if (DefInit *DI = dyn_cast<DefInit>(Rec)) {
Record *Def = DI->getDef();
const Record *Def = DI->getDef();
if (Def == CurRec)
PrintFatalError(CurRec->getLoc(),
Twine("Attempting to access field '") +
Expand Down Expand Up @@ -2656,7 +2656,7 @@ void DagInit::Profile(FoldingSetNodeID &ID) const {
ArrayRef(getTrailingObjects<StringInit *>(), NumArgNames));
}

Record *DagInit::getOperatorAsDef(ArrayRef<SMLoc> Loc) const {
const Record *DagInit::getOperatorAsDef(ArrayRef<SMLoc> Loc) const {
if (DefInit *DefI = dyn_cast<DefInit>(Val))
return DefI->getDef();
PrintFatalError(Loc, "Expected record as operator");
Expand Down Expand Up @@ -2837,8 +2837,8 @@ const RecordRecTy *Record::getType() const {

DefInit *Record::getDefInit() const {
if (!CorrespondingDefInit) {
CorrespondingDefInit = new (TrackedRecords.getImpl().Allocator)
DefInit(const_cast<Record *>(this));
CorrespondingDefInit =
new (TrackedRecords.getImpl().Allocator) DefInit(this);
}
return CorrespondingDefInit;
}
Expand Down Expand Up @@ -3108,7 +3108,7 @@ Record::getValueAsListOfStrings(StringRef FieldName) const {
return Strings;
}

Record *Record::getValueAsDef(StringRef FieldName) const {
const Record *Record::getValueAsDef(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (!R || !R->getValue())
PrintFatalError(getLoc(), "Record `" + getName() +
Expand All @@ -3120,7 +3120,7 @@ Record *Record::getValueAsDef(StringRef FieldName) const {
FieldName + "' does not have a def initializer!");
}

Record *Record::getValueAsOptionalDef(StringRef FieldName) const {
const Record *Record::getValueAsOptionalDef(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (!R || !R->getValue())
PrintFatalError(getLoc(), "Record `" + getName() +
Expand All @@ -3134,7 +3134,6 @@ Record *Record::getValueAsOptionalDef(StringRef FieldName) const {
FieldName + "' does not have either a def initializer or '?'!");
}


bool Record::getValueAsBit(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (!R || !R->getValue())
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/TableGen/TGParser.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3001,7 +3001,8 @@ Init *TGParser::ParseValue(Record *CurRec, const RecTy *ItemType,
// Add a reference to this field if we know the record class.
if (TrackReferenceLocs) {
if (auto *DI = dyn_cast<DefInit>(Result)) {
DI->getDef()->getValue(FieldName)->addReferenceLoc(FieldNameLoc);
const RecordVal *V = DI->getDef()->getValue(FieldName);
const_cast<RecordVal *>(V)->addReferenceLoc(FieldNameLoc);
} else if (auto *TI = dyn_cast<TypedInit>(Result)) {
if (auto *RecTy = dyn_cast<RecordRecTy>(TI->getType())) {
for (const Record *R : RecTy->getClasses())
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3698,7 +3698,7 @@ static bool hasNullFragReference(DagInit *DI) {
DefInit *OpDef = dyn_cast<DefInit>(DI->getOperator());
if (!OpDef)
return false;
Record *Operator = OpDef->getDef();
const Record *Operator = OpDef->getDef();

// If this is the null fragment, return true.
if (Operator->getName() == "null_frag")
Expand Down
38 changes: 19 additions & 19 deletions llvm/utils/TableGen/Common/CodeGenSchedule.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -552,7 +552,7 @@ void CodeGenSchedModels::addProcModel(const Record *ProcDef) {

std::string Name = std::string(ModelKey->getName());
if (ModelKey->isSubClassOf("SchedMachineModel")) {
Record *ItinsDef = ModelKey->getValueAsDef("Itineraries");
const Record *ItinsDef = ModelKey->getValueAsDef("Itineraries");
ProcModels.emplace_back(ProcModels.size(), Name, ModelKey, ItinsDef);
} else {
// An itinerary is defined without a machine model. Infer a new model.
Expand Down Expand Up @@ -674,9 +674,9 @@ void CodeGenSchedModels::collectSchedRW() {
}
// Initialize Aliases vectors.
for (const Record *ADef : AliasDefs) {
Record *AliasDef = ADef->getValueAsDef("AliasRW");
const Record *AliasDef = ADef->getValueAsDef("AliasRW");
getSchedRW(AliasDef).IsAlias = true;
Record *MatchDef = ADef->getValueAsDef("MatchRW");
const Record *MatchDef = ADef->getValueAsDef("MatchRW");
CodeGenSchedRW &RW = getSchedRW(MatchDef);
if (RW.IsAlias)
PrintFatalError(ADef->getLoc(), "Cannot Alias an Alias");
Expand Down Expand Up @@ -781,7 +781,7 @@ void CodeGenSchedModels::expandRWSeqForProc(
for (const Record *Rec : SchedWrite.Aliases) {
const CodeGenSchedRW &AliasRW = getSchedRW(Rec->getValueAsDef("AliasRW"));
if (Rec->getValueInit("SchedModel")->isComplete()) {
Record *ModelDef = Rec->getValueAsDef("SchedModel");
const Record *ModelDef = Rec->getValueAsDef("SchedModel");
if (&getProcModel(ModelDef) != &ProcModel)
continue;
}
Expand Down Expand Up @@ -854,7 +854,7 @@ void CodeGenSchedModels::collectSchedClasses() {
// Create a SchedClass for each unique combination of itinerary class and
// SchedRW list.
for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
const Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
IdxVec Writes, Reads;
if (!Inst->TheDef->isValueUnset("SchedRW"))
findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
Expand Down Expand Up @@ -1050,7 +1050,7 @@ void CodeGenSchedModels::createInstRWClass(const Record *InstRWDef) {
if (OrigNumInstrs == InstDefs.size()) {
assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
"expected a generic SchedClass");
Record *RWModelDef = InstRWDef->getValueAsDef("SchedModel");
const Record *RWModelDef = InstRWDef->getValueAsDef("SchedModel");
// Make sure we didn't already have a InstRW containing this
// instruction on this model.
for (const Record *RWD : RWDefs) {
Expand Down Expand Up @@ -1279,7 +1279,7 @@ struct PredCheck {
unsigned RWIdx;
const Record *Predicate;

PredCheck(bool r, unsigned w, Record *p)
PredCheck(bool r, unsigned w, const Record *p)
: IsRead(r), RWIdx(w), Predicate(p) {}
};

Expand Down Expand Up @@ -1318,7 +1318,7 @@ class PredTransitions {
#endif

private:
bool mutuallyExclusive(Record *PredDef, ArrayRef<Record *> Preds,
bool mutuallyExclusive(const Record *PredDef, ArrayRef<const Record *> Preds,
ArrayRef<PredCheck> Term);
void getIntersectingVariants(const CodeGenSchedRW &SchedRW, unsigned TransIdx,
std::vector<TransVariant> &IntersectingVariants);
Expand All @@ -1336,8 +1336,8 @@ class PredTransitions {
// predicates are not exclusive because the predicates for a given SchedWrite
// are always checked in the order they are defined in the .td file. Later
// conditions implicitly negate any prior condition.
bool PredTransitions::mutuallyExclusive(Record *PredDef,
ArrayRef<Record *> Preds,
bool PredTransitions::mutuallyExclusive(const Record *PredDef,
ArrayRef<const Record *> Preds,
ArrayRef<PredCheck> Term) {
for (const PredCheck &PC : Term) {
if (PC.Predicate == PredDef)
Expand Down Expand Up @@ -1382,9 +1382,9 @@ bool PredTransitions::mutuallyExclusive(Record *PredDef,
return false;
}

static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants,
unsigned ProcId) {
std::vector<Record *> Preds;
static std::vector<const Record *>
getAllPredicates(ArrayRef<TransVariant> Variants, unsigned ProcId) {
std::vector<const Record *> Preds;
for (auto &Variant : Variants) {
if (!Variant.VarOrSeqDef->isSubClassOf("SchedVar"))
continue;
Expand All @@ -1406,7 +1406,7 @@ void PredTransitions::getIntersectingVariants(
if (SchedRW.HasVariants) {
unsigned VarProcIdx = 0;
if (SchedRW.TheDef->getValueInit("SchedModel")->isComplete()) {
Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel");
const Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel");
VarProcIdx = SchedModels.getProcModel(ModelDef).Index;
}
if (VarProcIdx == 0 || VarProcIdx == TransVec[TransIdx].ProcIndex) {
Expand All @@ -1425,7 +1425,7 @@ void PredTransitions::getIntersectingVariants(
// that processor.
unsigned AliasProcIdx = 0;
if ((*AI)->getValueInit("SchedModel")->isComplete()) {
Record *ModelDef = (*AI)->getValueAsDef("SchedModel");
const Record *ModelDef = (*AI)->getValueAsDef("SchedModel");
AliasProcIdx = SchedModels.getProcModel(ModelDef).Index;
}
if (AliasProcIdx && AliasProcIdx != TransVec[TransIdx].ProcIndex)
Expand All @@ -1451,13 +1451,13 @@ void PredTransitions::getIntersectingVariants(
if (AliasProcIdx == 0)
GenericRW = true;
}
std::vector<Record *> AllPreds =
std::vector<const Record *> AllPreds =
getAllPredicates(Variants, TransVec[TransIdx].ProcIndex);
for (TransVariant &Variant : Variants) {
// Don't expand variants if the processor models don't intersect.
// A zero processor index means any processor.
if (Variant.VarOrSeqDef->isSubClassOf("SchedVar")) {
Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate");
const Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate");
if (mutuallyExclusive(PredDef, AllPreds, TransVec[TransIdx].PredTerm))
continue;
}
Expand Down Expand Up @@ -1489,7 +1489,7 @@ void PredTransitions::pushVariant(const TransVariant &VInfo, bool IsRead) {
// then the whole transition is specific to this processor.
IdxVec SelectedRWs;
if (VInfo.VarOrSeqDef->isSubClassOf("SchedVar")) {
Record *PredDef = VInfo.VarOrSeqDef->getValueAsDef("Predicate");
const Record *PredDef = VInfo.VarOrSeqDef->getValueAsDef("Predicate");
Trans.PredTerm.emplace_back(IsRead, VInfo.RWIdx, PredDef);
ConstRecVec SelectedDefs =
VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");
Expand Down Expand Up @@ -1861,7 +1861,7 @@ void CodeGenSchedModels::collectProcResources() {
// This class may have a default ReadWrite list which can be overriden by
// InstRW definitions.
for (const Record *RW : SC.InstRWs) {
Record *RWModelDef = RW->getValueAsDef("SchedModel");
const Record *RWModelDef = RW->getValueAsDef("SchedModel");
unsigned PIdx = getProcModel(RWModelDef).Index;
IdxVec Writes, Reads;
findRWs(RW->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/Common/GlobalISel/CombinerUtils.h
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ inline bool isSpecificDef(const Init &N, StringRef Def) {
/// subclass of the given class and coerce it to a def if it is. This is
/// primarily useful for testing for subclasses of GIDefKind and similar in
/// DagInit's since DagInit's support any type inside them.
inline Record *getDefOfSubClass(const Init &N, StringRef Cls) {
inline const Record *getDefOfSubClass(const Init &N, StringRef Cls) {
if (const DefInit *OpI = dyn_cast<DefInit>(&N))
if (OpI->getDef()->isSubClassOf(Cls))
return OpI->getDef();
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -1998,7 +1998,7 @@ class CopyOrAddZeroRegRenderer : public OperandRenderer {

public:
CopyOrAddZeroRegRenderer(unsigned NewInsnID, StringRef SymbolicName,
Record *ZeroRegisterDef)
const Record *ZeroRegisterDef)
: OperandRenderer(OR_CopyOrAddZeroReg), NewInsnID(NewInsnID),
SymbolicName(SymbolicName), ZeroRegisterDef(ZeroRegisterDef) {
assert(!SymbolicName.empty() && "Cannot copy from an unspecified source");
Expand Down
2 changes: 1 addition & 1 deletion mlir/include/mlir/TableGen/Attribute.h
Original file line number Diff line number Diff line change
Expand Up @@ -204,7 +204,7 @@ class EnumAttr : public Attribute {
std::vector<EnumAttrCase> getAllCases() const;

bool genSpecializedAttr() const;
llvm::Record *getBaseAttrClass() const;
const llvm::Record *getBaseAttrClass() const;
StringRef getSpecializedAttrClassName() const;
bool printBitEnumPrimaryGroups() const;
};
Expand Down
2 changes: 1 addition & 1 deletion mlir/lib/TableGen/Attribute.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -229,7 +229,7 @@ bool EnumAttr::genSpecializedAttr() const {
return def->getValueAsBit("genSpecializedAttr");
}

llvm::Record *EnumAttr::getBaseAttrClass() const {
const llvm::Record *EnumAttr::getBaseAttrClass() const {
return def->getValueAsDef("baseAttrClass");
}

Expand Down
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