diff --git a/pciedebug/build/doctrees/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.doctree b/pciedebug/build/doctrees/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.doctree index eecaefc7..087f968c 100644 Binary files a/pciedebug/build/doctrees/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.doctree and b/pciedebug/build/doctrees/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.doctree differ diff --git a/pciedebug/build/doctrees/environment.pickle b/pciedebug/build/doctrees/environment.pickle index 6ec0cfba..9a8b06ae 100644 Binary files a/pciedebug/build/doctrees/environment.pickle and b/pciedebug/build/doctrees/environment.pickle differ diff --git a/pciedebug/build/html/_sources/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.rst.txt b/pciedebug/build/html/_sources/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.rst.txt index 3ea0f3ec..742ae877 100644 --- a/pciedebug/build/html/_sources/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.rst.txt +++ b/pciedebug/build/html/_sources/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.rst.txt @@ -259,3 +259,123 @@ Important Design Considerations from PG344 - When prefetch mode is enabled, the user application cannot send credits as input in QDMA Descriptor Credit input ports. - In cache bypass mode, prefetch tag is maintained by the IP internally. Signal c2h_byp_out_pfch_tag[6:0] should be looped back as an input c2h_byp_in_st_csh_pfch_tag[6:0]. The prefetch tag points to the cam that stores the active queues in the prefetch engine. - No sequence is required between payload and completion packets. + +.. note:: + :class: highlight-box + + **Link**: `Handling Descriptors With Errors `_ + + - For a queue in bypass mode, it is the responsibility of the user logic to not issue a batch of descriptors with an error descriptor. Instead, it must send just one descriptor with error input asserted on the C2H Stream bypass-in interface and set the SOP, EOP, no_dma signal, and sdi or mrkr_req signal to make the C2H Stream Engine send a writeback to Host. + +.. note:: + :class: highlight-box + + **Link**: `Completion Engine `_ + + - Although not a requirement, a CMPT is typically used with a C2H queue. + - The user-defined portion of the CMPT packet typically needs to specify the length of the data packet transferred and whether or not descriptors were consumed as a result of the data packet transfer. + - Maximum buffer size register 0xB50 bits[31:26] is programmed to 0 (default value). This value might result in an overflow depending on the simulator or the synthesis tool used. To avoid overflow, set 0xB50 bits[31:26] to maximum value of 63. + +.. note:: + :class: highlight-box + + **Link**: `Completion Context Structure `_ + + - baddr4_low: Since the minimum alignment supported is 64B in this case, this field must be 0. + - pidx: Completion Ring Producer Index. This is a field written by the hardware. The software must initialize it to 0 and then treat it as read-only. Color bit to be used on Completion. + +.. note:: + :class: highlight-box + + **Link**: `Completion Status Structure `_ + + - In order to make the QDMA write Completion Status to the Completion ring, Completion Status must be enabled in the Completion context. + +.. note:: + :class: highlight-box + + **Link**: `Completion Status/Interrupt Moderation `_ + + - When in TRIGGER_EVERY, TRIGGER_USER, and TRIGGER_USER_COUNT mode, the software must read all the Completion entries in the Completion ring as indicated by an interrupt (or a Completion Status write). + +.. note:: + :class: highlight-box + + **Link**: `Address Translation `_ + + - When this option is selected, one full 64-bit BAR space is given for slave data transfer. You must set up any address translation if needed. If No Address Translation is not selected, DMA will do address translation. + +.. note:: + :class: highlight-box + + **Link**: `Slave Address Translation Examples `_ + + - The slave bridge does not support narrow burst AXI transfers. + +.. note:: + :class: highlight-box + + **Link**: `Legacy Interrupt `_ + + - To enable the legacy interrupt, the software needs to set the en_lgcy_intr bit in the register QDMA_GLBL_GLBL_INTERRUPT_CFG (0x2C4). + +.. note:: + :class: highlight-box + + **Link**: `Function Map Table `_ + + - Along with FMAP table programming in the IP, you must program the FMAP table in the Mailbox IP. This is needed for function level reset (FLR) procedure. + +.. note:: + :class: highlight-box + + **Link**: `Context Programming `_ + + - A host profile table context needs to be programmed before any context settings. + +.. note:: + :class: highlight-box + + **Link**: `Queue Setup `_ + + - If interrupts/status writes are desired (enabled in the Completion Context), an initial Completion CIDX update is required to send the hardware into a state where it is sensitive to trigger conditions. This initial CIDX update is required, because when out of reset, the hardware initializes into an unarmed state. + +.. note:: + :class: highlight-box + + **Link**: `Host Profile `_ + + - Host profile must be programmed to represent root port host. Host profile can be programmed through context programming. Select QDMA_CTXT_SELC_HOST_PROFILE (4'hA) in QDMA_IND_CTXT_CMD. + - H2C AXI4-MM steering bit and C2H AXI4-MM steering bit should be set to 0s. If not, DMA AXI4-MM transfers do not work. For most cases, host profile context structure is all 0s, and host profile must still be programmed to represent a host. + +.. note:: + :class: highlight-box + + **Link**: `Resets `_ + + - Reset the QDMA logic through the soft_reset_n port. This port needs to be held in reset for a minimum of 100 clock cycles (axi_aclk cycles). This does not reset PCIe hard block. It resets only the DMA portion of logic. This reset can be asserted if there is a DMA hang or some error condition. + - The use cases that prompt the use of soft_reset include: + - DMA hangs and user is not getting proper values. + - DMA transfers have errors, but the PCIe links are good. DMA records some asynchronous error. + - After soft_reset, you must reinitialize the queues and program all queue context. + +.. note:: + :class: highlight-box + + **Link**: `Expansion ROM `_ + + - The maximum size for the Expansion ROM BAR should be no larger than 16 MB. Selecting an address space larger than 16 MB can result in a non-compliant core. + +.. note:: + :class: highlight-box + + **Link**: `Data Path Errors `_ + + - Any DMA during and after the parity error should be considered invalid. If there is a parity error and transfer hangs or stops, the DMA will log the error. You must investigate and fix the parity issues. + +.. note:: + :class: highlight-box + + **Link**: `AXI Bridge Slave Ports `_ + + - The valid data identified by s_axib_wstrb must be continuous from the first byte enable to the last byte enable. diff --git a/pciedebug/build/html/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.html b/pciedebug/build/html/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.html index b9c92e7a..27d5c06b 100644 --- a/pciedebug/build/html/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.html +++ b/pciedebug/build/html/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.html @@ -386,6 +386,126 @@

  • No sequence is required between payload and completion packets.

    • +
    +

    Note

    +

    Link: Handling Descriptors With Errors

    +
      +

    • For a queue in bypass mode, it is the responsibility of the user logic to not issue a batch of descriptors with an error descriptor. Instead, it must send just one descriptor with error input asserted on the C2H Stream bypass-in interface and set the SOP, EOP, no_dma signal, and sdi or mrkr_req signal to make the C2H Stream Engine send a writeback to Host.

      • +
    +
    +
    +

    Note

    +

    Link: Completion Engine

    +
      +

    • Although not a requirement, a CMPT is typically used with a C2H queue.

      • +

    • The user-defined portion of the CMPT packet typically needs to specify the length of the data packet transferred and whether or not descriptors were consumed as a result of the data packet transfer.

      • +

    • Maximum buffer size register 0xB50 bits[31:26] is programmed to 0 (default value). This value might result in an overflow depending on the simulator or the synthesis tool used. To avoid overflow, set 0xB50 bits[31:26] to maximum value of 63.

      • +
    +
    +
    +

    Note

    +

    Link: Completion Context Structure

    +
      +

    • baddr4_low: Since the minimum alignment supported is 64B in this case, this field must be 0.

      • +

    • pidx: Completion Ring Producer Index. This is a field written by the hardware. The software must initialize it to 0 and then treat it as read-only. Color bit to be used on Completion.

      • +
    +
    +
    +

    Note

    +

    Link: Completion Status Structure

    +
      +

    • In order to make the QDMA write Completion Status to the Completion ring, Completion Status must be enabled in the Completion context.

      • +
    +
    +
    +

    Note

    +

    Link: Completion Status/Interrupt Moderation

    +
      +

    • When in TRIGGER_EVERY, TRIGGER_USER, and TRIGGER_USER_COUNT mode, the software must read all the Completion entries in the Completion ring as indicated by an interrupt (or a Completion Status write).

      • +
    +
    +
    +

    Note

    +

    Link: Address Translation

    +
      +

    • When this option is selected, one full 64-bit BAR space is given for slave data transfer. You must set up any address translation if needed. If No Address Translation is not selected, DMA will do address translation.

      • +
    +
    +
    +

    Note

    +

    Link: Slave Address Translation Examples

    +
      +

    • The slave bridge does not support narrow burst AXI transfers.

      • +
    +
    +
    +

    Note

    +

    Link: Legacy Interrupt

    +
      +

    • To enable the legacy interrupt, the software needs to set the en_lgcy_intr bit in the register QDMA_GLBL_GLBL_INTERRUPT_CFG (0x2C4).

      • +
    +
    +
    +

    Note

    +

    Link: Function Map Table

    +
      +

    • Along with FMAP table programming in the IP, you must program the FMAP table in the Mailbox IP. This is needed for function level reset (FLR) procedure.

      • +
    +
    +
    +

    Note

    +

    Link: Context Programming

    +
      +

    • A host profile table context needs to be programmed before any context settings.

      • +
    +
    +
    +

    Note

    +

    Link: Queue Setup

    +
      +

    • If interrupts/status writes are desired (enabled in the Completion Context), an initial Completion CIDX update is required to send the hardware into a state where it is sensitive to trigger conditions. This initial CIDX update is required, because when out of reset, the hardware initializes into an unarmed state.

      • +
    +
    +
    +

    Note

    +

    Link: Host Profile

    +
      +

    • Host profile must be programmed to represent root port host. Host profile can be programmed through context programming. Select QDMA_CTXT_SELC_HOST_PROFILE (4’hA) in QDMA_IND_CTXT_CMD.

      • +

    • H2C AXI4-MM steering bit and C2H AXI4-MM steering bit should be set to 0s. If not, DMA AXI4-MM transfers do not work. For most cases, host profile context structure is all 0s, and host profile must still be programmed to represent a host.

      • +
    +
    +
    +

    Note

    +

    Link: Resets

    +
      +

    • Reset the QDMA logic through the soft_reset_n port. This port needs to be held in reset for a minimum of 100 clock cycles (axi_aclk cycles). This does not reset PCIe hard block. It resets only the DMA portion of logic. This reset can be asserted if there is a DMA hang or some error condition.

      • +

    • The use cases that prompt the use of soft_reset include: +- DMA hangs and user is not getting proper values. +- DMA transfers have errors, but the PCIe links are good. DMA records some asynchronous error.

      • +

    • After soft_reset, you must reinitialize the queues and program all queue context.

      • +
    +
    +
    +

    Note

    +

    Link: Expansion ROM

    +
      +

    • The maximum size for the Expansion ROM BAR should be no larger than 16 MB. Selecting an address space larger than 16 MB can result in a non-compliant core.

      • +
    +
    +
    +

    Note

    +

    Link: Data Path Errors

    +
      +

    • Any DMA during and after the parity error should be considered invalid. If there is a parity error and transfer hangs or stops, the DMA will log the error. You must investigate and fix the parity issues.

      • +
    +
    +
    +

    Note

    +

    Link: AXI Bridge Slave Ports

    +
      +

    • The valid data identified by s_axib_wstrb must be continuous from the first byte enable to the last byte enable.

      • +
    +
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49, 50, 53, 54, 55, 62, 66, 67, 68, 72, 78, 79, 81, 85, 86, 90, 91, 92, 93, 97], "facilit": 4, "align": [4, 53, 70, 78], "address": [4, 6, 8, 10, 11, 25, 26, 32, 43, 53, 54, 62, 65, 70, 78, 97], "boundari": [4, 54, 55], "0": [4, 7, 10, 28, 29, 32, 48, 50, 53, 54, 55, 57, 65, 67, 74], "begin": [4, 53], "valid": [4, 48, 53, 54, 79], "cycl": [4, 11, 18, 32, 53, 54, 79], "appropri": [4, 53, 77], "calcul": [4, 53, 54], "offset": [4, 8, 10, 53, 77], "given": [4, 11, 18, 53, 54, 72, 76], "howev": [4, 16, 50, 53, 54, 78], "identifi": [4, 10, 19, 33, 53, 62, 77], "continu": [4, 16, 32, 53, 54, 62], "first": [4, 8, 19, 32, 33, 53, 55, 62, 70, 76, 77, 97], "byte": [4, 10, 11, 16, 53, 54, 55, 78], "enabl": [4, 8, 11, 14, 16, 18, 19, 32, 33, 48, 50, 53, 54, 60, 62, 65, 66, 67, 70, 77, 78, 82, 85, 91, 92, 96], "last": [4, 11, 53, 54, 55, 65, 79], "The": [4, 6, 8, 9, 10, 11, 14, 16, 18, 19, 29, 32, 33, 38, 48, 50, 53, 54, 55, 58, 61, 62, 63, 70, 72, 73, 77, 78, 79, 85, 87, 91, 92, 96], "core": [4, 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68, 72, 73, 77, 78, 79, 97], "without": [4, 6, 50, 53], "default": [4, 6, 15, 19, 22, 25, 33, 36, 53, 62, 78], "0x0000_0000": 4, "program": [4, 9, 24, 25, 27, 29, 32, 48, 50, 53, 54, 55, 60, 62, 65, 70, 77, 87], "separ": [4, 19, 33, 62, 77], "hit": [4, 70], "accord": [4, 19, 33], "outsid": [4, 67, 91], "rang": [4, 9, 48], "cannot": [4, 53, 54, 77], "recommend": [4, 9, 48, 53, 54, 62], "do": [4, 8, 14, 16, 19, 32, 33, 38, 48, 50, 53, 54, 55, 67, 72, 77, 78, 85, 91], "set_finite_credit": 4, "fals": [4, 77, 91], "infinit": [4, 79], "credit": [4, 14, 16, 19, 25, 32, 33, 53, 54, 55, 60, 62, 65, 66, 67, 70, 72, 79], "advertis": [4, 48], "complex": [4, 26, 29, 51, 90], "finit": 4, "requir": [4, 18, 19, 25, 32, 33, 43, 48, 50, 53, 54, 55, 62, 68, 70, 77, 91, 97], "most": [4, 19, 33, 53, 54], "obei": [4, 54], "caution": 4, "verifi": [4, 19, 25, 33, 60], "function": [4, 14, 48, 53, 54, 55, 66, 70, 78, 92], "output": [4, 14, 19, 24, 27, 33, 53, 54, 60, 67, 70, 72, 77, 87, 92], "s_axi_arreadi": 4, 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56, 62, 68, 73, 78, 79, 81, 85, 86, 91, 93, 97], "gotcha": [5, 13, 56, 60, 81, 93, 97], "gener": [5, 11, 13, 14, 20, 25, 26, 29, 34, 43, 49, 51, 53, 54, 56, 60, 62, 71, 73, 81, 86, 93], "checklist": [5, 13, 20, 34, 49, 60, 71, 81, 86, 93, 97], "tip": [5, 13, 31, 49, 81, 86, 97], "question": [5, 13, 20, 34, 49, 72, 81, 86, 97], "collater": [5, 13, 20, 34, 49, 56, 81, 86, 93, 97], "between": [6, 10, 19, 33, 53, 54, 58], "d0": 6, "uniniti": 6, "state": [6, 8, 19, 32, 33, 50, 53, 54, 62, 78, 82, 85, 91, 92], "mean": [6, 32, 53, 67], "physic": [6, 53, 54, 66, 77], "hasn": [6, 55], "t": [6, 19, 33, 50, 55, 77], "exchang": [6, 32], "initfc": 6, "enumer": [6, 9, 14, 19, 33, 48, 85, 97], "thu": [6, 62, 77, 79], "get": [6, 14, 16, 53, 54, 60, 72, 74, 77, 82, 85], "through": [6, 8, 10, 24, 25, 27, 32, 50, 53, 54, 55, 62, 65, 70, 73, 78], "essenti": [6, 53, 54], "user_reset": 6, "releas": [6, 7, 15, 31, 48, 51, 53, 57, 83, 95, 97], "layer": 6, "should": [6, 9, 10, 16, 19, 32, 33, 48, 50, 53, 54, 55, 62, 65, 70, 72, 73, 77, 78, 79], "therefor": [6, 53, 54], "indic": [6, 11, 14, 18, 19, 32, 33, 53, 54, 62, 92], "send": [6, 16, 53, 54, 55, 62, 67, 72, 76], "over": [6, 11, 53, 54, 79], "usabl": 6, "host": [6, 11, 16, 19, 25, 32, 33, 53, 54, 62, 65, 70, 78, 85, 87, 91], "testbench": 6, "hang": [6, 14, 53, 54, 70], "memori": [6, 10, 15, 16, 19, 24, 25, 26, 27, 32, 33, 48, 53, 54, 60, 62, 67, 70, 78, 85, 92], "whether": [6, 19, 32, 33, 38, 53], "non": [6, 9, 19, 33, 48, 50, 53, 54, 77, 79], "exist": [6, 19, 32, 33, 91], "These": [6, 72, 77], "attempt": [6, 19, 33], "would": [6, 16, 50, 53, 54], "readi": [6, 53, 54, 79], "mechan": [6, 11, 25, 59, 97], "unlik": [6, 48], "A": [6, 11, 19, 25, 33, 51, 53, 54, 62, 76, 88], "possibl": [6, 10, 16, 19, 33, 38, 53, 54, 62, 91], "workaround": 6, "firewal": 6, "outstand": [6, 53, 54, 62, 79], "number": [6, 9, 16, 28, 48, 53, 54, 55, 58, 62, 66, 67, 70, 72, 79], "8": [6, 10, 25, 26, 50, 53, 54, 90], "c_s_axi_num_read": 6, "one": [6, 11, 18, 32, 53, 54, 76], "instead": [6, 16, 19, 32, 33, 53, 54, 62, 78, 91], "narow": 6, "event": [6, 54], "though": [6, 67], "limit": [6, 16, 50, 53, 54, 91], "masteraxi": 6, "descript": [7, 15, 18, 19, 22, 33, 36, 51, 57, 60, 76, 78, 83, 88, 95], "url": [7, 15, 18, 22, 36, 51, 57, 76, 83, 88, 95], "v3": [7, 57], "http": [7, 15, 16, 18, 19, 22, 24, 27, 29, 30, 33, 36, 38, 48, 50, 51, 53, 55, 57, 58, 61, 68, 70, 73, 74, 76, 78, 83, 85, 88, 90, 91, 95], "www": [7, 15, 18, 19, 22, 24, 27, 29, 30, 33, 36, 38, 48, 50, 51, 57, 76, 78, 83, 85, 88, 91, 95], "xilinx": [7, 9, 15, 16, 18, 19, 22, 24, 25, 26, 27, 28, 29, 30, 33, 36, 38, 48, 50, 51, 55, 57, 62, 67, 68, 70, 74, 76, 78, 83, 85, 88, 90, 91, 95], "com": [7, 15, 16, 18, 19, 22, 24, 27, 29, 30, 33, 36, 38, 48, 50, 51, 53, 55, 57, 58, 61, 70, 73, 74, 76, 78, 83, 85, 88, 90, 91, 95], "ip_document": [7, 15, 83], "axi_pcie3": 7, "v3_0": 7, "pdf": [7, 15, 19, 22, 24, 27, 30, 33, 36, 76, 83, 88, 95], "xdma": [7, 9, 10, 11, 14, 15, 25, 26, 29, 48, 57, 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54], "correspond": [4, 8, 19, 33, 53, 54, 67, 73, 76, 79], "mask": [4, 19, 33, 66, 67], "also": [4, 16, 18, 53, 54, 55, 62, 65, 77, 78, 79, 85], "set": [4, 6, 8, 9, 14, 19, 32, 33, 48, 50, 53, 54, 55, 62, 66, 67, 69, 72, 73, 76, 82, 87, 91], "avail": [4, 14, 16, 19, 33, 39, 40, 41, 42, 44, 45, 46, 47, 50, 53, 55, 62, 65, 69, 72, 91], "dma": [4, 10, 14, 15, 16, 24, 25, 26, 27, 28, 29, 50, 53, 54, 55, 57, 60, 62, 65, 66, 68, 72, 74, 76, 77, 97], "option": [4, 9, 16, 19, 33, 48, 53, 54, 66, 78, 79, 96], "dma_bridge_resetn": 4, "input": [4, 19, 24, 27, 32, 33, 53, 54, 55, 60, 62, 70, 76], "pin": [4, 9, 11, 18, 19, 32, 33, 48, 77, 91], "which": [4, 6, 14, 16, 19, 33, 50, 53, 54, 55, 62, 67, 70, 78], "allow": [4, 19, 33, 53, 54, 62, 79], "you": [4, 8, 11, 14, 16, 18, 19, 32, 33, 38, 48, 53, 54, 62, 67, 72, 79, 92], "all": [4, 11, 19, 28, 32, 33, 53, 54, 55, 60, 62, 66, 67, 70, 72, 74, 76, 77, 78], "intern": [4, 7, 8, 10, 15, 26, 53, 54, 55, 60, 62, 66, 67, 72], "engin": [4, 53, 54, 60, 61, 62, 65, 72], "well": [4, 19, 33, 50, 62, 65, 85, 91], "peripher": [4, 6], "driven": [4, 32, 53, 54, 76], "axi_aresetn": [4, 6, 70], "axi_ctl_aresetn": 4, "when": [4, 6, 9, 11, 14, 32, 48, 50, 53, 54, 55, 62, 66, 67, 70, 76, 77, 79, 92, 97], "paramet": [4, 8, 10, 19, 33, 60, 73], "need": [4, 11, 18, 50, 53, 54, 55, 62, 72, 73, 92], "dure": [4, 11, 32, 48, 50, 53, 54, 62, 77, 79], "initi": [4, 9, 10, 14, 16, 24, 27, 48, 50, 53, 54, 58, 60, 65, 77], "link": [4, 5, 6, 13, 14, 16, 24, 25, 26, 27, 32, 48, 49, 50, 53, 54, 55, 58, 61, 62, 68, 73, 74, 78, 79, 81, 85, 86, 90, 91, 92, 93, 97], "up": [4, 6, 8, 9, 14, 16, 32, 38, 48, 50, 53, 54, 55, 62, 78, 85], "oper": [4, 9, 48, 50, 53, 54, 62], "becaus": [4, 6, 8, 53, 54, 55, 62, 73], "done": [4, 6, 9, 11, 18, 32, 48, 50, 53, 54, 55, 62, 67, 70, 72, 77, 87, 91], "automat": [4, 91], "ip": [4, 6, 7, 9, 11, 14, 15, 16, 18, 19, 24, 25, 26, 27, 29, 33, 48, 53, 54, 55, 57, 60, 61, 67, 70, 73, 76, 77, 78, 82, 85, 91, 95, 96, 97], "must": [4, 8, 11, 32, 48, 53, 54, 62, 72, 77, 78, 79], "termin": [4, 11, 19, 33], "transact": [4, 6, 8, 25, 53, 62, 76, 78], "befor": [4, 6, 8, 14, 28, 48, 50, 53, 54, 55, 62, 70, 85, 91], "thi": [4, 6, 8, 11, 14, 16, 18, 19, 32, 33, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 50, 53, 54, 55, 62, 67, 70, 72, 73, 77, 78, 79, 85, 87, 91, 92, 96], "after": [4, 6, 8, 19, 32, 33, 53, 54, 62, 67, 70, 77, 79, 91, 97], "being": [4, 9, 16, 19, 32, 33, 48, 50, 53, 54, 62, 67, 71, 72, 76, 97], "kept": 4, "minimum": [4, 19, 33, 53, 54], "durat": [4, 79], "least": [4, 53], "equal": [4, 6, 19, 33, 53, 54], "complet": [4, 8, 16, 25, 53, 54, 55, 60, 62, 65, 66, 67, 70, 72, 77, 78, 79, 97], "timeout": [4, 6, 62, 67, 76, 92, 97], "valu": [4, 9, 14, 16, 19, 33, 48, 50, 53, 54, 58, 62, 67, 70, 72, 74, 77, 79, 92], "typic": [4, 11, 16, 32, 53, 54], "50": 4, "m": [4, 50, 77], "clear": [4, 11, 19, 33, 53, 54, 62, 70], "ani": [4, 6, 8, 16, 19, 33, 53, 54, 55, 62, 63, 67, 72, 73, 76, 78, 79, 92], "pend": [4, 8, 11, 53, 60], "transfer": [4, 10, 11, 14, 16, 53, 54, 60, 62, 63, 70, 72, 74, 79], "mai": [4, 19, 33, 62], "current": [4, 53, 54, 55, 62, 91], "queu": 4, "data": [4, 6, 8, 11, 16, 19, 33, 53, 54, 55, 60, 62, 63, 66, 78, 79, 87, 97], "path": [4, 19, 33, 53, 54], "To": [4, 10, 38, 48, 53, 54, 55, 62, 78, 85, 91], "type": [4, 6, 11, 19, 33, 53, 66, 73, 79], "command": [4, 9, 11, 14, 18, 32, 48, 50, 67, 78, 91, 92], "tcl": [4, 11, 38, 55, 77, 91], "set_properti": [4, 11, 77, 91], "dict": [4, 11], "list": [4, 11, 19, 29, 32, 33, 53, 54, 67, 76], "config": [4, 6, 10, 11, 19, 24, 27, 32, 33, 77, 91], "soft_reset_en": 4, "true": [4, 11, 19, 33, 55, 77, 91], "get_ip": [4, 11, 91], "ip_nam": [4, 11], "request": [4, 6, 8, 11, 50, 53, 54, 55, 62, 78, 79, 97], "length": [4, 6, 11, 53, 54, 55, 66], "greater": [4, 6, 50], "than": [4, 6, 11, 16, 32, 50, 53, 54, 62, 72, 78, 79], "1": [4, 6, 7, 8, 10, 11, 14, 15, 19, 22, 25, 26, 29, 32, 33, 36, 48, 50, 53, 55, 57, 60, 67, 70, 77, 78, 79, 83, 90], "dword": [4, 6, 78], "size": [4, 6, 11, 16, 32, 53, 54, 55, 58, 62, 67, 70, 72, 79], "burst": [4, 6, 16, 53, 54], "alwai": [4, 6, 11, 53, 54, 60, 62, 67, 76], "width": [4, 6, 11, 16, 19, 33, 38, 53, 78, 79, 92], "bu": [4, 6, 9, 24, 27, 32, 48, 50, 54, 62, 78, 79, 92], "even": [4, 6, 11, 53, 67, 77], "receiv": [4, 6, 18, 50, 53, 54, 62, 79, 97], "shorter": [4, 6], "s_axi_wstrb": 4, "can": [4, 6, 8, 9, 11, 16, 19, 32, 33, 38, 48, 50, 53, 54, 55, 58, 62, 72, 73, 77, 78, 79, 87, 91, 96], "us": [4, 5, 6, 9, 10, 11, 13, 14, 16, 19, 20, 24, 25, 26, 27, 29, 32, 33, 34, 38, 48, 49, 50, 53, 54, 55, 62, 66, 67, 68, 72, 78, 79, 81, 85, 86, 90, 91, 92, 93, 97], "facilit": 4, "align": [4, 53, 54, 70, 78], "address": [4, 6, 8, 10, 11, 25, 26, 32, 43, 53, 54, 62, 65, 70, 78, 97], "boundari": [4, 54, 55], "0": [4, 7, 10, 28, 29, 32, 48, 50, 53, 54, 55, 57, 65, 67, 74], "begin": [4, 53], "valid": [4, 48, 53, 54, 79], "cycl": [4, 11, 18, 32, 53, 54, 79], "appropri": [4, 53, 77], "calcul": [4, 53, 54], "offset": [4, 8, 10, 53, 77], "given": [4, 11, 18, 53, 54, 72, 76], "howev": [4, 16, 50, 53, 54, 78], "identifi": [4, 10, 19, 33, 53, 54, 62, 77], "continu": [4, 16, 32, 53, 54, 62], "first": [4, 8, 19, 32, 33, 53, 54, 55, 62, 70, 76, 77, 97], "byte": [4, 10, 11, 16, 53, 54, 55, 78], "enabl": [4, 8, 11, 14, 16, 18, 19, 32, 33, 48, 50, 53, 54, 60, 62, 65, 66, 67, 70, 77, 78, 82, 85, 91, 92, 96], "last": [4, 11, 53, 54, 55, 65, 79], "The": [4, 6, 8, 9, 10, 11, 14, 16, 18, 19, 29, 32, 33, 38, 48, 50, 53, 54, 55, 58, 61, 62, 63, 70, 72, 73, 77, 78, 79, 85, 87, 91, 92, 96], "core": [4, 14, 19, 24, 26, 27, 29, 33, 53, 54, 73, 77, 79, 88, 95], "conform": 4, "order": [4, 8, 32, 53, 54, 72, 73], "rule": [4, 8, 19, 33], "pci": [4, 7, 9, 15, 16, 18, 19, 22, 24, 25, 26, 27, 28, 29, 30, 32, 33, 36, 48, 50, 51, 57, 58, 76, 77, 78, 82, 83, 85, 88, 91, 92, 95], "sig": [4, 29], "specif": [4, 5, 9, 19, 33, 48, 93, 97], "behavior": [4, 20, 34, 53, 97], "ar": [4, 8, 9, 10, 11, 14, 16, 18, 19, 28, 32, 33, 48, 50, 53, 54, 55, 62, 65, 66, 67, 70, 72, 73, 74, 76, 77, 78, 79, 85, 87, 91], "implement": [4, 11, 20, 29, 34, 53, 62, 70, 97], "enforc": 4, "highli": 4, "parallel": 4, "bresp": [4, 8, 62], "remot": 4, "until": [4, 18, 53, 77, 79], "memwr": 4, "tlp": [4, 6, 78, 79, 97], "transmiss": [4, 19, 33], "guarante": [4, 53, 54], "sent": [4, 11, 53, 54, 62, 71, 97], "subsequ": [4, 58], "tx": [4, 19, 33, 53, 76], "relax": [4, 32], "within": [4, 10, 11, 16, 18, 19, 32, 33, 50, 53, 54, 77, 79], "header": 4, "permit": 4, "pass": [4, 29, 53, 54, 55], "previou": [4, 8, 19, 33, 91], "phase": [4, 19, 33, 62, 76, 85], "held": [4, 18, 54], "have": [4, 8, 16, 19, 32, 33, 38, 50, 53, 54, 55, 62, 72, 85], "ha": [4, 8, 9, 10, 11, 14, 18, 19, 32, 33, 48, 50, 53, 54, 62, 72, 73, 77, 78, 79], "been": [4, 6, 9, 11, 14, 19, 32, 33, 48, 55, 72, 73, 77, 85], "attribut": [4, 78], "prior": [4, 8, 28, 53, 54, 62], "": [4, 6, 11, 15, 16, 19, 25, 26, 32, 33, 48, 50, 55, 57, 58, 62, 70, 73, 90], "present": [4, 53, 54], "channel": [4, 10, 16, 19, 33, 91], "integr": [4, 14, 16, 18, 19, 22, 24, 25, 26, 27, 28, 32, 33, 36, 38, 62, 76, 77, 78, 79, 82, 83, 85, 91, 95, 97], "block": [4, 11, 18, 19, 22, 24, 25, 26, 27, 28, 33, 36, 50, 53, 54, 55, 62, 72, 76, 77, 78, 79, 82, 83, 85, 91, 95, 96, 97], "express": [4, 7, 9, 15, 16, 18, 19, 22, 24, 25, 26, 27, 28, 29, 30, 33, 36, 38, 48, 51, 57, 58, 76, 77, 78, 82, 83, 85, 88, 91, 95], "detect": [4, 11, 14, 32, 50, 55, 62, 70, 71, 78, 85, 87, 91, 97], "malform": 4, "configur": [4, 9, 11, 16, 18, 20, 24, 25, 27, 29, 34, 48, 53, 54, 60, 62, 67, 70, 76, 77, 78, 79, 85, 87, 92, 97], "result": [4, 6, 53, 54, 62], "fatal": [4, 50, 55], "messag": [4, 25, 77], "upstream": [4, 78], "report": [4, 48, 50, 55, 57, 67, 70], "monitor": [4, 25, 53, 55], "ensur": [4, 8, 11, 16, 18, 19, 32, 33, 50, 53, 54, 62, 76], "onli": [4, 6, 10, 11, 16, 18, 19, 25, 33, 38, 50, 53, 54, 55, 60, 62, 65, 67, 78, 79, 90, 91], "incr": [4, 53], "increment": [4, 53, 62], "other": [4, 8, 19, 33, 50, 53, 54, 76], "treat": [4, 54, 79], "condit": [4, 53, 54], "illeg": 4, "sib": 4, "In": [4, 6, 19, 24, 25, 27, 33, 38, 50, 53, 54, 55, 62, 73, 74, 78, 87, 91], "case": [4, 19, 26, 33, 38, 53, 54, 55, 62, 68, 78], "slverr": 4, "beat": [4, 11, 53, 54, 79], "arbitrari": 4, "place": [4, 19, 32, 33, 53, 77], "s_axi_rdata": 4, "respons": [4, 6, 10, 14, 25, 53, 54, 62, 66, 67, 72], "discard": 4, "normal": [4, 62], "depend": [4, 6, 8, 11, 53, 54, 62, 70, 73, 79], "establish": [4, 6, 48], "maintain": [4, 53, 54, 62, 65, 77], "point": [4, 19, 33, 53, 54, 55], "extern": [4, 53, 54, 87, 96], "lost": [4, 32, 62], "re": [4, 32, 77, 78, 85, 91], "return": [4, 6, 32, 85], "hot": [4, 18, 50], "goe": [4, 50, 62, 73, 78, 85, 91], "down": [4, 14, 19, 32, 33, 50, 62, 67], "space": [4, 10, 18, 19, 25, 32, 33, 48, 51, 53, 54, 62, 65, 78, 88, 92], "reconfigur": [4, 24, 27, 77], "yet": 4, "associ": [4, 50, 53, 54, 55, 62, 70], "start": [4, 50, 53, 54, 62, 77, 79, 85], "bar": [4, 8, 9, 16, 19, 32, 33, 48, 53, 54, 66, 85], "support": [4, 7, 10, 11, 15, 16, 18, 19, 22, 24, 27, 30, 33, 36, 38, 43, 48, 50, 51, 53, 54, 55, 57, 68, 70, 76, 78, 83, 85, 88, 90, 91, 95, 97], "filter": [4, 77], "forward": [4, 8], "translat": [4, 8, 9, 25, 48, 53, 54], "disabl": [4, 6, 9, 11, 16, 18, 19, 32, 33, 48, 50, 53, 54, 62, 66, 78, 92], "custom": [4, 16, 19, 25, 33, 53, 55, 67, 77, 91], "design": [4, 9, 10, 11, 15, 16, 20, 22, 24, 25, 26, 27, 28, 29, 30, 32, 34, 36, 48, 51, 56, 62, 67, 68, 70, 72, 73, 77, 78, 83, 85, 86, 91, 96, 97], "suit": [4, 28, 76], "rp": [4, 19, 33, 50], "applic": [4, 11, 16, 31, 32, 53, 54, 62, 67, 68, 72, 73, 77, 78, 79, 97], "without": [4, 6, 50, 53], "default": [4, 6, 15, 19, 22, 25, 33, 36, 53, 54, 62, 78], "0x0000_0000": 4, "program": [4, 9, 24, 25, 27, 29, 32, 48, 50, 53, 54, 55, 60, 62, 65, 70, 77, 87], "separ": [4, 19, 33, 62, 77], "hit": [4, 70], "accord": [4, 19, 33], "outsid": [4, 67, 91], "rang": [4, 9, 48], "cannot": [4, 53, 54, 77], "recommend": [4, 9, 48, 53, 54, 62], "do": [4, 8, 14, 16, 19, 32, 33, 38, 48, 50, 53, 54, 55, 67, 72, 77, 78, 85, 91], "set_finite_credit": 4, "fals": [4, 77, 91], "infinit": [4, 79], "credit": [4, 14, 16, 19, 25, 32, 33, 53, 54, 55, 60, 62, 65, 66, 67, 70, 72, 79], "advertis": [4, 48], "complex": [4, 26, 29, 51, 90], "finit": 4, "requir": [4, 18, 19, 25, 32, 33, 43, 48, 50, 53, 54, 55, 62, 68, 70, 77, 91, 97], "most": [4, 19, 33, 53, 54], "obei": [4, 54], "caution": 4, "verifi": [4, 19, 25, 33, 60], "function": [4, 14, 48, 53, 54, 55, 66, 70, 78, 92], "output": [4, 14, 19, 24, 27, 33, 53, 54, 60, 67, 70, 72, 77, 87, 92], "s_axi_arreadi": 4, "s_axi_rvalid": 4, "unrespons": 4, "met": [4, 24, 27], "older": 4, "axi_ctl_aclk": 4, "axi_ctl_aclk_out": 4, "puls": 4, "out": [4, 10, 19, 25, 32, 33, 53, 54, 55, 63, 87, 96], "activ": [4, 54, 70, 77, 79], "low": [4, 53, 54, 62], "main": [4, 16], "toggl": [4, 70], "simul": [4, 19, 24, 25, 26, 27, 29, 33, 53, 54, 70, 90, 97], "run": [4, 9, 19, 25, 29, 32, 33, 48, 50, 53, 54, 62, 67, 78, 85, 91], "featur": [4, 14, 19, 22, 25, 26, 33, 36, 53, 54, 55, 62, 66, 77, 78, 83, 85, 91], "captur": [4, 10, 19, 33, 78, 85], "waveform": 4, "access": [4, 6, 14, 48, 53, 54, 70, 77], "abov": [4, 11, 19, 50, 53, 54, 61, 62, 78, 79, 85], "taken": [4, 11, 19, 33, 62, 79], "qdma": [4, 15, 25, 26, 29, 38, 53, 54, 55, 57, 62, 63, 67, 70, 72, 76, 79, 90, 96], "product": [4, 7, 11, 16, 18, 53, 54, 62, 78, 79, 83, 88, 95], "guid": [4, 11, 15, 16, 18, 19, 22, 25, 26, 33, 36, 48, 51, 53, 54, 57, 62, 78, 79, 83, 85, 88, 91, 95], "pg195": [4, 10, 11, 12, 15], "document": [4, 5, 11, 13, 19, 20, 24, 27, 30, 33, 34, 43, 56, 62, 68, 73, 78, 79, 81, 85, 86, 91, 93, 97], "gotcha": [5, 13, 56, 60, 81, 93, 97], "gener": [5, 11, 13, 14, 20, 25, 26, 29, 34, 43, 49, 51, 53, 54, 56, 60, 62, 71, 73, 81, 86, 93], "checklist": [5, 13, 20, 34, 49, 60, 71, 81, 86, 93, 97], "tip": [5, 13, 31, 49, 81, 86, 97], "question": [5, 13, 20, 34, 49, 72, 81, 86, 97], "collater": [5, 13, 20, 34, 49, 56, 81, 86, 93, 97], "between": [6, 10, 19, 33, 53, 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b/pciedebug/source/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.rst index 3ea0f3ec..742ae877 100644 --- a/pciedebug/source/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.rst +++ b/pciedebug/source/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.rst @@ -259,3 +259,123 @@ Important Design Considerations from PG344 - When prefetch mode is enabled, the user application cannot send credits as input in QDMA Descriptor Credit input ports. - In cache bypass mode, prefetch tag is maintained by the IP internally. Signal c2h_byp_out_pfch_tag[6:0] should be looped back as an input c2h_byp_in_st_csh_pfch_tag[6:0]. The prefetch tag points to the cam that stores the active queues in the prefetch engine. - No sequence is required between payload and completion packets. + +.. note:: + :class: highlight-box + + **Link**: `Handling Descriptors With Errors `_ + + - For a queue in bypass mode, it is the responsibility of the user logic to not issue a batch of descriptors with an error descriptor. Instead, it must send just one descriptor with error input asserted on the C2H Stream bypass-in interface and set the SOP, EOP, no_dma signal, and sdi or mrkr_req signal to make the C2H Stream Engine send a writeback to Host. + +.. note:: + :class: highlight-box + + **Link**: `Completion Engine `_ + + - Although not a requirement, a CMPT is typically used with a C2H queue. + - The user-defined portion of the CMPT packet typically needs to specify the length of the data packet transferred and whether or not descriptors were consumed as a result of the data packet transfer. + - Maximum buffer size register 0xB50 bits[31:26] is programmed to 0 (default value). This value might result in an overflow depending on the simulator or the synthesis tool used. To avoid overflow, set 0xB50 bits[31:26] to maximum value of 63. + +.. note:: + :class: highlight-box + + **Link**: `Completion Context Structure `_ + + - baddr4_low: Since the minimum alignment supported is 64B in this case, this field must be 0. + - pidx: Completion Ring Producer Index. This is a field written by the hardware. The software must initialize it to 0 and then treat it as read-only. Color bit to be used on Completion. + +.. note:: + :class: highlight-box + + **Link**: `Completion Status Structure `_ + + - In order to make the QDMA write Completion Status to the Completion ring, Completion Status must be enabled in the Completion context. + +.. note:: + :class: highlight-box + + **Link**: `Completion Status/Interrupt Moderation `_ + + - When in TRIGGER_EVERY, TRIGGER_USER, and TRIGGER_USER_COUNT mode, the software must read all the Completion entries in the Completion ring as indicated by an interrupt (or a Completion Status write). + +.. note:: + :class: highlight-box + + **Link**: `Address Translation `_ + + - When this option is selected, one full 64-bit BAR space is given for slave data transfer. You must set up any address translation if needed. If No Address Translation is not selected, DMA will do address translation. + +.. note:: + :class: highlight-box + + **Link**: `Slave Address Translation Examples `_ + + - The slave bridge does not support narrow burst AXI transfers. + +.. note:: + :class: highlight-box + + **Link**: `Legacy Interrupt `_ + + - To enable the legacy interrupt, the software needs to set the en_lgcy_intr bit in the register QDMA_GLBL_GLBL_INTERRUPT_CFG (0x2C4). + +.. note:: + :class: highlight-box + + **Link**: `Function Map Table `_ + + - Along with FMAP table programming in the IP, you must program the FMAP table in the Mailbox IP. This is needed for function level reset (FLR) procedure. + +.. note:: + :class: highlight-box + + **Link**: `Context Programming `_ + + - A host profile table context needs to be programmed before any context settings. + +.. note:: + :class: highlight-box + + **Link**: `Queue Setup `_ + + - If interrupts/status writes are desired (enabled in the Completion Context), an initial Completion CIDX update is required to send the hardware into a state where it is sensitive to trigger conditions. This initial CIDX update is required, because when out of reset, the hardware initializes into an unarmed state. + +.. note:: + :class: highlight-box + + **Link**: `Host Profile `_ + + - Host profile must be programmed to represent root port host. Host profile can be programmed through context programming. Select QDMA_CTXT_SELC_HOST_PROFILE (4'hA) in QDMA_IND_CTXT_CMD. + - H2C AXI4-MM steering bit and C2H AXI4-MM steering bit should be set to 0s. If not, DMA AXI4-MM transfers do not work. For most cases, host profile context structure is all 0s, and host profile must still be programmed to represent a host. + +.. note:: + :class: highlight-box + + **Link**: `Resets `_ + + - Reset the QDMA logic through the soft_reset_n port. This port needs to be held in reset for a minimum of 100 clock cycles (axi_aclk cycles). This does not reset PCIe hard block. It resets only the DMA portion of logic. This reset can be asserted if there is a DMA hang or some error condition. + - The use cases that prompt the use of soft_reset include: + - DMA hangs and user is not getting proper values. + - DMA transfers have errors, but the PCIe links are good. DMA records some asynchronous error. + - After soft_reset, you must reinitialize the queues and program all queue context. + +.. note:: + :class: highlight-box + + **Link**: `Expansion ROM `_ + + - The maximum size for the Expansion ROM BAR should be no larger than 16 MB. Selecting an address space larger than 16 MB can result in a non-compliant core. + +.. note:: + :class: highlight-box + + **Link**: `Data Path Errors `_ + + - Any DMA during and after the parity error should be considered invalid. If there is a parity error and transfer hangs or stops, the DMA will log the error. You must investigate and fix the parity issues. + +.. note:: + :class: highlight-box + + **Link**: `AXI Bridge Slave Ports `_ + + - The valid data identified by s_axib_wstrb must be continuous from the first byte enable to the last byte enable.