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Set port_id for Verific PortBus wires #5442

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Set port_id for Verific PortBus wires #5442

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1 change: 1 addition & 0 deletions frontends/verific/verific.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1576,6 +1576,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
SetIter si ;
Port *port ;
FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
wire->port_id = nl->IndexOf(port) + 1;
import_attributes(wire->attributes, port->GetNet(), nl, portbus->Size());
break;
}
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13 changes: 13 additions & 0 deletions tests/verific/port_bus_order.ys
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@@ -0,0 +1,13 @@
verific -sv <<EOT
module simple (
input [3:0] I2,
input [3:0] I1,
output [3:0] result
);
assign result = I2 & I1;
endmodule
EOT
verific -import simple

write_verilog verilog_port_bus_order.out
!grep -qF 'simple(I2, I1, result)' verilog_port_bus_order.out
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